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Class Information
Number: 257/E21.585
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Filling of holes, grooves, vias or trenches with conductive material (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C4.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.587 By deposition over sacrificial masking layer, e.g., lift-off (epo) 162
257/E21.586 By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (epo) 641
257/E21.588 Reflowing or applying pressure to fill contact hole, e.g., to remove voids (epo) 236


Patents under this class:
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Patent Number Title Of Patent Date Issued
7294571 Concave pattern formation method and method for forming semiconductor device Nov. 13, 2007
7294570 Contact integration method Nov. 13, 2007
7282445 Multiple seed layers for interconnects Oct. 16, 2007
7282442 Contact hole structure of semiconductor device and method of forming the same Oct. 16, 2007
7279750 Semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion Oct. 9, 2007
7276438 Method of manufacturing wiring substrate Oct. 2, 2007
7276434 Method for filling a contact hole having a small diameter and a large aspect ratio Oct. 2, 2007
7273811 Method for chemical vapor deposition in high aspect ratio spaces Sep. 25, 2007
7268390 Power semiconductor device Sep. 11, 2007
7268072 Method and structure for reducing contact aspect ratios Sep. 11, 2007
7262461 JFET and MESFET structures for low voltage, high current and high frequency applications Aug. 28, 2007
7259093 Methods of forming a conductive contact through a dielectric Aug. 21, 2007
7256124 Method of fabricating semiconductor device Aug. 14, 2007
7247897 Conductive line for a semiconductor device using a carbon nanotube including a memory thin film and semiconductor device manufactured Jul. 24, 2007
7235474 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts Jun. 26, 2007
7232746 Method for forming dual damascene interconnection in semiconductor device Jun. 19, 2007
7229916 Method of manufacturing a semiconductor device Jun. 12, 2007
7229878 Phototransistor of CMOS image sensor and method for fabricating the same Jun. 12, 2007
7227265 Electroplated copper interconnection structure, process for making and electroplating bath Jun. 5, 2007
7226858 Submicron contact fill using a CVD TiN barrier and high temperature PVD aluminum alloy deposition Jun. 5, 2007
7217655 Electroplated CoWP composite structures as copper barrier layers May. 15, 2007
7215028 Semiconductor device and method for fabricating the same May. 8, 2007
7214611 Imprinting-damascene process for metal interconnection May. 8, 2007
7214610 Process for producing aluminum-filled contact holes May. 8, 2007
7211496 Freestanding multiplayer IC wiring structure May. 1, 2007
7205208 Method of manufacturing a semiconductor device Apr. 17, 2007
7199450 Materials and method to seal vias in silicon substrates Apr. 3, 2007
7199050 Pass through via technology for use during the manufacture of a semiconductor device Apr. 3, 2007
7199045 Metal-filled openings for submicron devices and methods of manufacture thereof Apr. 3, 2007
7193327 Barrier structure for semiconductor devices Mar. 20, 2007
7189642 Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components Mar. 13, 2007
7189641 Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers Mar. 13, 2007
7183609 Semiconductor devices and methods for fabricating the same Feb. 27, 2007
7183196 Multilayer interconnection board and production method thereof Feb. 27, 2007
7180192 Semiconductor device Feb. 20, 2007
7179732 Interconnection structure and fabrication method thereof Feb. 20, 2007
7163894 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same Jan. 16, 2007
7160801 Integrated circuit using a dual poly process Jan. 9, 2007
7118953 Process of fabricating termination region for trench MIS device Oct. 10, 2006
7115502 Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process Oct. 3, 2006
7074709 Localized doping and/or alloying of metallization for increased interconnect performance Jul. 11, 2006
7074714 Method of depositing a metal seed layer on semiconductor substrates Jul. 11, 2006
7074721 Method for forming thick copper self-aligned dual damascene Jul. 11, 2006
7075182 Semiconductor device Jul. 11, 2006
7071055 Method of forming a contact structure including a vertical barrier structure and two barrier layers Jul. 4, 2006
7071508 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and semiconductor constructions Jul. 4, 2006
7071558 Agglomeration control using early transition metal alloys Jul. 4, 2006
7067416 Method of forming a conductive contact Jun. 27, 2006
7064056 Barrier layer stack to prevent Ti diffusion Jun. 20, 2006
7064068 Method to improve planarity of electroplated copper Jun. 20, 2006

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