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Class Information
Number: 257/E21.585
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Filling of holes, grooves, vias or trenches with conductive material (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C4.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7625819 |
Interconnection process |
Dec. 1, 2009 |
| 7625818 |
Method for forming vias in a substrate |
Dec. 1, 2009 |
| 7622375 |
Conductive member and process of producing the same |
Nov. 24, 2009 |
| 7615486 |
Apparatus and method for integrated surface treatment and deposition for copper interconnect |
Nov. 10, 2009 |
| 7615475 |
Method for fabricating landing polysilicon contact structures for semiconductor devices |
Nov. 10, 2009 |
| 7611985 |
Formation of holes in substrates using dewetting coatings |
Nov. 3, 2009 |
| 7602055 |
Semiconductor device and method for fabricating the same |
Oct. 13, 2009 |
| 7601637 |
Atomic layer deposited tantalum containing adhesion layer |
Oct. 13, 2009 |
| 7595556 |
Semiconductor device and method for manufacturing the same |
Sep. 29, 2009 |
| 7595529 |
Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same |
Sep. 29, 2009 |
| 7592267 |
Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same |
Sep. 22, 2009 |
| 7592259 |
Methods and systems for barrier layer surface passivation |
Sep. 22, 2009 |
| 7592258 |
Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same |
Sep. 22, 2009 |
| 7592248 |
Method of forming semiconductor device having nanotube structures |
Sep. 22, 2009 |
| 7592245 |
Poly filled substrate contact on SOI structure |
Sep. 22, 2009 |
| 7589014 |
Semiconductor device having multiple wiring layers and method of producing the same |
Sep. 15, 2009 |
| 7582566 |
Method for redirecting void diffusion away from vias in an integrated circuit design |
Sep. 1, 2009 |
| 7576004 |
Semiconductor chip and method of manufacturing semiconductor chip |
Aug. 18, 2009 |
| 7576002 |
Multi-step barrier deposition method |
Aug. 18, 2009 |
| 7572717 |
Method of manufacturing semiconductor device |
Aug. 11, 2009 |
| 7566653 |
Interconnect structure with grain growth promotion layer and method for forming the same |
Jul. 28, 2009 |
| 7566621 |
Method for forming semiconductor device having fin structure |
Jul. 28, 2009 |
| 7563719 |
Dual damascene process |
Jul. 21, 2009 |
| 7557039 |
Method for fabricating contact hole of semiconductor device |
Jul. 7, 2009 |
| 7557036 |
Method, system, and apparatus for filling vias |
Jul. 7, 2009 |
| 7557034 |
Semiconductor device and a method of manufacturing the same |
Jul. 7, 2009 |
| 7553763 |
Salicide process utilizing a cluster ion implantation process |
Jun. 30, 2009 |
| 7553743 |
Wafer bonding method of system in package |
Jun. 30, 2009 |
| 7550386 |
Advanced seed layers for interconnects |
Jun. 23, 2009 |
| 7547972 |
Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof |
Jun. 16, 2009 |
| 7547628 |
Method for manufacturing capacitor |
Jun. 16, 2009 |
| 7541279 |
Method for manufacturing semiconductor device |
Jun. 2, 2009 |
| 7531896 |
Semiconductor device having a minimal via resistance created by applying a nitrogen plasma to a titanium via liner |
May. 12, 2009 |
| 7524742 |
Structure of metal interconnect and fabrication method thereof |
Apr. 28, 2009 |
| 7524716 |
Fabricating method of semiconductor structure |
Apr. 28, 2009 |
| 7521368 |
Method for manufacturing semiconductor device |
Apr. 21, 2009 |
| 7521352 |
Method for manufacturing a semiconductor device |
Apr. 21, 2009 |
| 7517782 |
Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase |
Apr. 14, 2009 |
| 7514309 |
Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process |
Apr. 7, 2009 |
| 7501687 |
Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation |
Mar. 10, 2009 |
| 7501342 |
Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same |
Mar. 10, 2009 |
| 7498260 |
Pass through via technology for use during the manufacture of a semiconductor device |
Mar. 3, 2009 |
| 7498254 |
Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
Mar. 3, 2009 |
| 7498253 |
Local interconnection method and structure for use in semiconductor device |
Mar. 3, 2009 |
| 7498252 |
Dual layer dielectric stack for microelectronics having thick metal lines |
Mar. 3, 2009 |
| 7494927 |
Method of growing electrical conductors |
Feb. 24, 2009 |
| 7491560 |
Fabricating method of flat panel display device |
Feb. 17, 2009 |
| 7485560 |
Method for fabricating crystalline silicon thin films |
Feb. 3, 2009 |
| 7482694 |
Semiconductor device and its manufacturing method |
Jan. 27, 2009 |
| 7482198 |
Method for producing through-contacts and a semiconductor component with through-contacts |
Jan. 27, 2009 |
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