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Class Information
Number: 257/E21.583
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Planarization; smoothing (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C2.


Patents under this class:
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Patent Number Title Of Patent Date Issued
7582565 Method and apparatus for semiconductor wafer planarization Sep. 1, 2009
7566653 Interconnect structure with grain growth promotion layer and method for forming the same Jul. 28, 2009
7560380 Chemical dissolution of barrier and adhesion layers Jul. 14, 2009
7557025 Method of etching a dielectric layer to form a contact hole and a via hole and damascene method Jul. 7, 2009
7550748 Apparatus and methods for systematic non-uniformity correction using a gas cluster ion beam Jun. 23, 2009
7541279 Method for manufacturing semiconductor device Jun. 2, 2009
7541625 Semiconductor integrated circuit Jun. 2, 2009
7510972 Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device Mar. 31, 2009
7507657 Method for fabricating storage node contact in semiconductor device Mar. 24, 2009
7452816 Semiconductor processing method and chemical mechanical polishing methods Nov. 18, 2008
7453152 Device having reduced chemical mechanical planarization Nov. 18, 2008
7446415 Method for filling electrically different features Nov. 4, 2008
7439125 Contact structure for a stack DRAM storage capacitor Oct. 21, 2008
7427561 Method for manufacturing semiconductor device Sep. 23, 2008
7422982 Method and apparatus for electroprocessing a substrate with edge profile control Sep. 9, 2008
7417321 Via structure and process for forming the same Aug. 26, 2008
7381638 Fabrication technique using sputter etch and vacuum transfer Jun. 3, 2008
7348676 Semiconductor device having a metal wiring structure Mar. 25, 2008
7300877 Method of manufacturing a semiconductor device Nov. 27, 2007
7211512 Selective electroless-plated copper metallization May. 1, 2007
7208831 Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer Apr. 24, 2007
7205208 Method of manufacturing a semiconductor device Apr. 17, 2007
7195700 Method of electroplating copper layers with flat topography Mar. 27, 2007
7186574 CMP process metrology test structures Mar. 6, 2007
7163894 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same Jan. 16, 2007
7138340 Method for fabricating semiconductor device without damaging hard mask during contact formation process Nov. 21, 2006
7105925 Differential planarization Sep. 12, 2006
7071108 Chemical mechanical polishing slurry containing abrasive particles exhibiting photocatalytic function Jul. 4, 2006
7071539 Chemical planarization performance for copper/low-k interconnect structures Jul. 4, 2006
7067920 Semiconductor device and method of fabricating the same Jun. 27, 2006
7067919 Semiconductor device Jun. 27, 2006
7064057 Method and apparatus for localized material removal by electrochemical polishing Jun. 20, 2006
7064053 Process for fabricating an electrical circuit comprising a polishing step Jun. 20, 2006
7064068 Method to improve planarity of electroplated copper Jun. 20, 2006
7060606 Method and apparatus for chemical mechanical polishing of semiconductor substrates Jun. 13, 2006
7060619 Reduction of the shear stress in copper via's in organic interlayer dielectric material Jun. 13, 2006
RE39126 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs Jun. 13, 2006
7060618 Semiconductor device, method for manufacturing the same, and plating solution Jun. 13, 2006
7056826 Method of forming copper interconnects Jun. 6, 2006
7053462 Planarization of metal container structures May. 30, 2006
7049237 Methods for planarization of Group VIII metal-containing surfaces using oxidizing gases May. 23, 2006
7045454 Chemical mechanical planarization of conductive material May. 16, 2006
7045898 Semiconductor device and manufacturing method thereof May. 16, 2006
7045450 Method of manufacturing semiconductor device May. 16, 2006
7041586 Semiconductor device having a multilayer interconnection structure May. 9, 2006
7042099 Semiconductor device containing a dummy wire May. 9, 2006
7029591 Planarization with reduced dishing Apr. 18, 2006
7030044 Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric Apr. 18, 2006
7022598 Method of producing multilayer interconnection structure Apr. 4, 2006
7018924 CMP slurry compositions for oxide films and methods for forming metal line contact plugs using the same Mar. 28, 2006

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