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Class Information
Number: 257/E21.583
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Planarization; smoothing (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C2.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8691597 Method for manufacturing a semiconductor device including application of a plating voltage Apr. 8, 2014
8673768 Fabrication method for improving surface planarity after tungsten chemical mechanical polishing Mar. 18, 2014
8653663 Barrier layer for copper interconnect Feb. 18, 2014
8617985 High temperature tungsten metallization process Dec. 31, 2013
8551874 MOSFET gate and source/drain contact metallization Oct. 8, 2013
8518818 Reverse damascene process Aug. 27, 2013
8450197 Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces May. 28, 2013
8445360 Method for manufacturing semiconductor device May. 21, 2013
8445382 Side wall pore sealing for low-k dielectrics May. 21, 2013
8432045 Conductive pads defined by embedded traces Apr. 30, 2013
8404582 Structure and method for manufacturing interconnect structures having self-aligned dielectric caps Mar. 26, 2013
8299625 Borderless interconnect line structure self-aligned to upper and lower level contact vias Oct. 30, 2012
8129268 Self-aligned lower bottom electrode Mar. 6, 2012
8124525 Method of forming self-aligned local interconnect and structure formed thereby Feb. 28, 2012
8084356 Methods of low-K dielectric and metal process integration Dec. 27, 2011
8072070 Low fabrication cost, fine pitch and high reliability solder bump Dec. 6, 2011
8048803 Method for forming contact plug in a semiconductor device Nov. 1, 2011
8043870 CMP pad thickness and profile monitoring system Oct. 25, 2011
8039397 Using optical metrology for within wafer feed forward process control Oct. 18, 2011
8034705 Method of forming a seam-free tungsten plug Oct. 11, 2011
8030209 Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer Oct. 4, 2011
7964907 Integrated circuit device gate structures Jun. 21, 2011
7960188 Polishing method Jun. 14, 2011
7960821 Dummy vias for damascene process Jun. 14, 2011
7956466 Structure for interconnect structure containing various capping materials for electrical fuse and other related applications Jun. 7, 2011
7952146 Grain growth promotion layer for semiconductor interconnect structures May. 31, 2011
7867870 Semiconductor device and method for forming device isolation film of semiconductor device Jan. 11, 2011
7824951 Method of fabricating an integrated circuit having a memory including a low-k dielectric material Nov. 2, 2010
7811927 Method of manufacturing metal line Oct. 12, 2010
7803693 Bowed wafer hybridization compensation Sep. 28, 2010
7795096 Method of forming an integrated circuit with two types of transistors Sep. 14, 2010
7767570 Dummy vias for damascene process Aug. 3, 2010
7727891 Method of manufacturing a semiconductor device using a wet process Jun. 1, 2010
7709344 Integrated circuit fabrication process using gas cluster ion beam etching May. 4, 2010
7704856 Semiconductor device, wiring substrate forming method, and substrate processing apparatus Apr. 27, 2010
7696086 Fabricating method of an interconnect structure Apr. 13, 2010
7670915 Contact liner in integrated circuit technology Mar. 2, 2010
7626183 Methods for modifying features of a workpiece using a gas cluster ion beam Dec. 1, 2009
7582565 Method and apparatus for semiconductor wafer planarization Sep. 1, 2009
7566653 Interconnect structure with grain growth promotion layer and method for forming the same Jul. 28, 2009
7560380 Chemical dissolution of barrier and adhesion layers Jul. 14, 2009
7557025 Method of etching a dielectric layer to form a contact hole and a via hole and damascene method Jul. 7, 2009
7550748 Apparatus and methods for systematic non-uniformity correction using a gas cluster ion beam Jun. 23, 2009
7541625 Semiconductor integrated circuit Jun. 2, 2009
7541279 Method for manufacturing semiconductor device Jun. 2, 2009
7510972 Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device Mar. 31, 2009
7507657 Method for fabricating storage node contact in semiconductor device Mar. 24, 2009
7452816 Semiconductor processing method and chemical mechanical polishing methods Nov. 18, 2008
7453152 Device having reduced chemical mechanical planarization Nov. 18, 2008
7446415 Method for filling electrically different features Nov. 4, 2008

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