| |
 |
|
Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6881665 |
Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist |
Apr. 19, 2005 |
| 6881678 |
Method for forming a dual damascene structure in a semiconductor device |
Apr. 19, 2005 |
| 6881999 |
Semiconductor device with analog capacitor and method of fabricating the same |
Apr. 19, 2005 |
| 6878619 |
Method for fabricating semiconductor device |
Apr. 12, 2005 |
| 6878621 |
Method of fabricating barrierless and embedded copper damascene interconnects |
Apr. 12, 2005 |
| 6879046 |
Split barrier layer including nitrogen-containing portion and oxygen-containing portion |
Apr. 12, 2005 |
| 6875688 |
Method for reactive ion etch processing of a dual damascene structure |
Apr. 5, 2005 |
| 6875699 |
Method for patterning multilevel interconnects |
Apr. 5, 2005 |
| 6876017 |
Polymer sacrificial light absorbing structure and method |
Apr. 5, 2005 |
| 6872665 |
Process flow for dual damescene interconnect structures |
Mar. 29, 2005 |
| 6872666 |
Method for making a dual damascene interconnect using a dual hard mask |
Mar. 29, 2005 |
| 6873052 |
Porous, film, wiring structure, and method of forming the same |
Mar. 29, 2005 |
| 6869870 |
High performance system-on-chip discrete components using post passivation process |
Mar. 22, 2005 |
| 6869873 |
Copper silicide passivation for improved reliability |
Mar. 22, 2005 |
| 6869888 |
E-beam flood exposure of spin-on material to eliminate voids in vias |
Mar. 22, 2005 |
| 6869896 |
Plasma processes for depositing low dielectric constant films |
Mar. 22, 2005 |
| 6870263 |
Device interconnection |
Mar. 22, 2005 |
| 6870265 |
Semiconductor device and manufacturing method thereof |
Mar. 22, 2005 |
| 6861329 |
Method of manufacturing capacitor in semiconductor devices |
Mar. 1, 2005 |
| 6861347 |
Method for forming metal wiring layer of semiconductor device |
Mar. 1, 2005 |
| 6861348 |
Pre-pattern surface modification of low-k dielectrics |
Mar. 1, 2005 |
| 6861376 |
Photoresist scum free process for via first dual damascene process |
Mar. 1, 2005 |
| 6861686 |
Structure of a CMOS image sensor and method for fabricating the same |
Mar. 1, 2005 |
| 6858153 |
Integrated low K dielectrics and etch stops |
Feb. 22, 2005 |
| 6858377 |
Dual damascene process using a single photo mask |
Feb. 22, 2005 |
| 6858528 |
Composite sacrificial material |
Feb. 22, 2005 |
| 6858549 |
Method for forming wiring structure |
Feb. 22, 2005 |
| 6855484 |
Method of depositing low dielectric constant silicon carbide layers |
Feb. 15, 2005 |
| 6855629 |
Method for forming a dual damascene wiring pattern in a semiconductor device |
Feb. 15, 2005 |
| 6855634 |
Polishing method and polishing apparatus |
Feb. 15, 2005 |
| 6856019 |
Semiconductor integrated circuit device |
Feb. 15, 2005 |
| 6856501 |
Capacitor having copper electrodes and diffusion barrier layers |
Feb. 15, 2005 |
| 6852619 |
Dual damascene semiconductor devices |
Feb. 8, 2005 |
| 6852635 |
Method for bottomless deposition of barrier layers in integrated circuit metallization schemes |
Feb. 8, 2005 |
| 6852647 |
Removable amorphous carbon CMP stop |
Feb. 8, 2005 |
| 6853003 |
Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same |
Feb. 8, 2005 |
| 6853043 |
Nitrogen-free antireflective coating for use with photolithographic patterning |
Feb. 8, 2005 |
| 6849387 |
Method for integrating copper process and MIM capacitor for embedded DRAM |
Feb. 1, 2005 |
| 6849536 |
Inter-metal dielectric patterns and method of forming the same |
Feb. 1, 2005 |
| 6849541 |
Method of fabricating a dual damascene copper wire |
Feb. 1, 2005 |
| 6849923 |
Semiconductor device and manufacturing method of the same |
Feb. 1, 2005 |
| 6846741 |
Sacrificial metal spacer damascene process |
Jan. 25, 2005 |
| 6846756 |
Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers |
Jan. 25, 2005 |
| 6844143 |
Sandwich photoresist structure in photolithographic process |
Jan. 18, 2005 |
| 6844255 |
Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
Jan. 18, 2005 |
| 6844257 |
Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens |
Jan. 18, 2005 |
| 6844266 |
Anisotropic etching of organic-containing insulating layers |
Jan. 18, 2005 |
| 6844267 |
Anisotropic etching of organic-containing insulating layers |
Jan. 18, 2005 |
| 6841341 |
Method of depositing an amorphous carbon layer |
Jan. 11, 2005 |
| 6841465 |
Method of forming dual damascene pattern in semiconductor device |
Jan. 11, 2005 |
|
|
|
