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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6930045 |
Cross reference to related application |
Aug. 16, 2005 |
| 6930052 |
Method for producing an integrated circuit having at least one metalicized surface |
Aug. 16, 2005 |
| 6930056 |
Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure |
Aug. 16, 2005 |
| 6930061 |
Plasma processes for depositing low dielectric constant films |
Aug. 16, 2005 |
| 6930394 |
Electronic device includes an insulating film having density or carbon concentration varying gradually in the direction of the thickness and a conductive film formed therein |
Aug. 16, 2005 |
| 6927161 |
Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique |
Aug. 9, 2005 |
| 6927178 |
Nitrogen-free dielectric anti-reflective coating and hardmask |
Aug. 9, 2005 |
| 6924221 |
Integrated process flow to improve copper filling in a damascene structure |
Aug. 2, 2005 |
| 6924228 |
Method of forming a via contact structure using a dual damascene technique |
Aug. 2, 2005 |
| 6921689 |
Method of manufacturing a capacitor with copper electrodes and diffusion barriers |
Jul. 26, 2005 |
| 6921978 |
Method to generate porous organic dielectric |
Jul. 26, 2005 |
| 6919266 |
Copper technology for ULSI metallization |
Jul. 19, 2005 |
| 6916724 |
Semiconductor device and method for manufacturing the same |
Jul. 12, 2005 |
| 6917108 |
Reliable low-k interconnect structure with hybrid dielectric |
Jul. 12, 2005 |
| 6913992 |
Method of modifying interlayer adhesion |
Jul. 5, 2005 |
| 6913994 |
Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects |
Jul. 5, 2005 |
| 6914320 |
Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof |
Jul. 5, 2005 |
| 6914335 |
Semiconductor device having a low-K dielectric layer |
Jul. 5, 2005 |
| 6911372 |
Method of fabricating storage capacitor in semiconductor memory device, and storage capacitor structure |
Jun. 28, 2005 |
| 6911389 |
Self aligned vias in dual damascene interconnect, buried mask approach |
Jun. 28, 2005 |
| 6911397 |
Method of forming dual damascene interconnection using low-k dielectric |
Jun. 28, 2005 |
| 6908846 |
Method and apparatus for detecting endpoint during plasma etching of thin films |
Jun. 21, 2005 |
| 6908847 |
Method of manufacturing a semiconductor device having an interconnect embedded in an insulating film |
Jun. 21, 2005 |
| 6908854 |
Method of forming a dual-layer resist and application thereof |
Jun. 21, 2005 |
| 6909190 |
Dual-damascene dielectric structures |
Jun. 21, 2005 |
| 6909195 |
Trench etch process for low-k dielectrics |
Jun. 21, 2005 |
| 6905909 |
Ultra low dielectric constant thin film |
Jun. 14, 2005 |
| 6905968 |
Process for selectively etching dielectric layers |
Jun. 14, 2005 |
| 6903461 |
Semiconductor device having a region of a material which is vaporized upon exposing to ultraviolet radiation |
Jun. 7, 2005 |
| 6898851 |
Electronic device manufacturing method |
May. 31, 2005 |
| 6900123 |
BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control |
May. 31, 2005 |
| 6900125 |
Method of manufacturing a semiconductor device including a multi-layer interconnect structure |
May. 31, 2005 |
| 6900140 |
Anisotropic etching of organic-containing insulating layers |
May. 31, 2005 |
| 6897145 |
Method for fabricating semiconductor device by forming damascene interconnections |
May. 24, 2005 |
| 6893954 |
Method for patterning a semiconductor wafer |
May. 17, 2005 |
| 6893956 |
Barrier layer for a copper metallization layer including a low-k dielectric |
May. 17, 2005 |
| 6894104 |
Anti-reflective coatings and dual damascene fill compositions comprising styrene-allyl alcohol copolymers |
May. 17, 2005 |
| 6894364 |
Capacitor in an interconnect system and method of manufacturing thereof |
May. 17, 2005 |
| 6890817 |
Method of manufacturing a semiconductor device with capacitor electrodes |
May. 10, 2005 |
| 6890848 |
Fabrication process of a semiconductor device |
May. 10, 2005 |
| 6890850 |
Method of depositing dielectric materials in damascene applications |
May. 10, 2005 |
| 6890864 |
Semiconductor device fabricating method and treating liquid |
May. 10, 2005 |
| 6890865 |
Low k film application for interlevel dielectric and method of cleaning etched features |
May. 10, 2005 |
| 6890869 |
Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof |
May. 10, 2005 |
| 6887780 |
Concentration graded carbon doped oxide |
May. 3, 2005 |
| 6887783 |
Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof |
May. 3, 2005 |
| 6887802 |
Method of manufacturing semiconductor device and semiconductor device |
May. 3, 2005 |
| 6888251 |
Metal spacer in single and dual damascene processing |
May. 3, 2005 |
| 6884710 |
Semiconductor device having multi-layer copper line and method of forming same |
Apr. 26, 2005 |
| 6884728 |
Method for removing polymeric residue contamination on semiconductor feature sidewalls |
Apr. 26, 2005 |
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