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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.


Patents under this class:

Patent Number Title Of Patent Date Issued
6977229 Manufacturing method for semiconductor devices Dec. 20, 2005
6977438 Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer Dec. 20, 2005
6974762 Adhesion of carbon doped oxides by silanization Dec. 13, 2005
6974766 In situ deposition of a low .kappa. dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application Dec. 13, 2005
6975033 Semiconductor device and method for manufacturing the same Dec. 13, 2005
RE38914 Dual damascene patterned conductor layer formation method without etch stop layer Dec. 6, 2005
6972251 Method for fabricating copper damascene structures in porous dielectric materials Dec. 6, 2005
6972253 Method for forming dielectric barrier layer in damascene structure Dec. 6, 2005
6972254 Manufacturing a conformal atomic liner layer in an integrated circuit interconnect Dec. 6, 2005
6972258 Method for selectively controlling damascene CD bias Dec. 6, 2005
6972259 Method for forming openings in low dielectric constant material layer Dec. 6, 2005
6969683 Method of preventing resist poisoning in dual damascene structures Nov. 29, 2005
6967156 Method to fabricate aligned dual damascene openings Nov. 22, 2005
6967165 Method for fabricating multilayer interconnect and method for checking the same Nov. 22, 2005
6967407 Semiconductor device and method of manufacturing the semiconductor device Nov. 22, 2005
6964874 Void formation monitoring in a damascene process Nov. 15, 2005
6964919 Low-k dielectric film with good mechanical strength Nov. 15, 2005
6965165 Top layers of metal for high performance IC's Nov. 15, 2005
6962727 Organosiloxanes Nov. 8, 2005
6962870 Method of manufacturing semiconductor device and semiconductor device Nov. 8, 2005
6962874 Method for fabricating semiconductor device Nov. 8, 2005
6962879 Method of plasma etching silicon nitride Nov. 8, 2005
6958294 Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization Oct. 25, 2005
6958547 Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs Oct. 25, 2005
6951809 Method for manufacturing semiconductor device Oct. 4, 2005
6951826 Silicon carbide deposition for use as a low dielectric constant anti-reflective coating Oct. 4, 2005
6949203 System level in-situ integrated dielectric etch process particularly useful for copper dual damascene Sep. 27, 2005
6949456 Method for manufacturing semiconductor device having porous structure with air-gaps Sep. 27, 2005
6949829 Semiconductor device and fabrication method therefor Sep. 27, 2005
6949830 Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device Sep. 27, 2005
6946381 Method of forming insulating film in semiconductor device Sep. 20, 2005
6946383 Method for forming wiring structure which includes annealing conductive film before and after removal of a portion of the conductive film Sep. 20, 2005
6946385 Production method for semiconductor device Sep. 20, 2005
6946391 Method for forming dual damascenes Sep. 20, 2005
6946401 Plasma treatment for copper oxide reduction Sep. 20, 2005
6943121 Selectively converted inter-layer dielectric Sep. 13, 2005
6943431 Semiconductor device using low-k material as interlayer insulating film and including a surface modifying layer Sep. 13, 2005
6939793 Dual damascene integration scheme for preventing copper contamination of dielectric layer Sep. 6, 2005
6939797 Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof Sep. 6, 2005
6939798 Method for forming T-shaped conductor wires of semiconductor device Sep. 6, 2005
6940170 Techniques for triple and quadruple damascene fabrication Sep. 6, 2005
6936408 Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer Aug. 30, 2005
6936531 Process of fabricating a chip structure Aug. 30, 2005
6936533 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer Aug. 30, 2005
6936534 Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization Aug. 30, 2005
6933230 Method for making interconnects and diffusion barriers in integrated circuits Aug. 23, 2005
6933586 Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens Aug. 23, 2005
6930033 Treating surface of low-dielectric constant material to achieve good mechanical strength Aug. 16, 2005
6930034 Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence Aug. 16, 2005
6930036 Semiconductor device and method of manufacturing the same Aug. 16, 2005



 
 
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