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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7034409 |
Method of eliminating photoresist poisoning in damascene applications |
Apr. 25, 2006 |
| 7029927 |
Method of repairing an integrated electronic circuit using a formed electrical isolation |
Apr. 18, 2006 |
| 7030007 |
Via-filling material and process for fabricating semiconductor integrated circuit using the material |
Apr. 18, 2006 |
| 7030010 |
Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures |
Apr. 18, 2006 |
| 7030023 |
Method for simultaneous degas and baking in copper damascene process |
Apr. 18, 2006 |
| 7030028 |
Etching method |
Apr. 18, 2006 |
| 7030031 |
Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
Apr. 18, 2006 |
| 7026052 |
Porous low k(<2.0) thin film derived from homo-transport-polymerization |
Apr. 11, 2006 |
| 7026237 |
Fill material for dual damascene processes |
Apr. 11, 2006 |
| 7026714 |
Copper interconnect systems which use conductive, metal-based cap layers |
Apr. 11, 2006 |
| 7026715 |
Semiconductor device having wiring layer formed in wiring groove |
Apr. 11, 2006 |
| 7021320 |
Method of removing a via fence |
Apr. 4, 2006 |
| 7022600 |
Method of forming dual damascene interconnection using low-k dielectric material |
Apr. 4, 2006 |
| 7022602 |
Nitrogen-enriched low-k barrier layer for a copper metallization layer |
Apr. 4, 2006 |
| 7022610 |
Wet cleaning method to eliminate copper corrosion |
Apr. 4, 2006 |
| 7022619 |
Method for fabricating electronic device |
Apr. 4, 2006 |
| 7023092 |
Low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds |
Apr. 4, 2006 |
| 7018918 |
Method of forming a selectively converted inter-layer dielectric using a porogen material |
Mar. 28, 2006 |
| 7018919 |
Method of manufacturing a semiconductor integrated circuit device including a hole formed in an insulating film and a first conductive film formed over a bottom region and sidewalls of the hol |
Mar. 28, 2006 |
| 7018920 |
Composite sacrificial material |
Mar. 28, 2006 |
| 7015137 |
Semiconductor device with reduced interconnection capacity |
Mar. 21, 2006 |
| 7011889 |
Organosiloxanes |
Mar. 14, 2006 |
| 7012022 |
Self-patterning of photo-active dielectric materials for interconnect isolation |
Mar. 14, 2006 |
| 7012335 |
Semiconductor device wiring and method of manufacturing the same |
Mar. 14, 2006 |
| 7008872 |
Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures |
Mar. 7, 2006 |
| 7005375 |
Method to avoid copper contamination of a via or dual damascene structure |
Feb. 28, 2006 |
| 7005390 |
Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
Feb. 28, 2006 |
| 7001836 |
Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers |
Feb. 21, 2006 |
| 7001839 |
Semiconductor device with tapered contact hole and wire groove |
Feb. 21, 2006 |
| 7001847 |
Micro pattern forming method and semiconductor device manufacturing method |
Feb. 21, 2006 |
| 7001850 |
Method of depositing dielectric films |
Feb. 21, 2006 |
| 7002201 |
Semiconductor device and manufacturing method thereof |
Feb. 21, 2006 |
| 7002252 |
Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure |
Feb. 21, 2006 |
| 7001529 |
Pre-endpoint techniques in photoresist etching |
Feb. 21, 2006 |
| 6998216 |
Mechanically robust interconnect for low-k dielectric material using post treatment |
Feb. 14, 2006 |
| 6995073 |
Air gap integration |
Feb. 7, 2006 |
| 6995085 |
Underlayer protection for the dual damascene etching |
Feb. 7, 2006 |
| 6995087 |
Integrated circuit with simultaneous fabrication of dual damascene via and trench |
Feb. 7, 2006 |
| 6992344 |
Damascene integration scheme for developing metal-insulator-metal capacitors |
Jan. 31, 2006 |
| 6992391 |
Dual-damascene interconnects without an etch stop layer by alternating ILDs |
Jan. 31, 2006 |
| 6989595 |
Molds configured to pattern masses associated with semiconductor constructions |
Jan. 24, 2006 |
| 6989604 |
Conformal barrier liner in an integrated circuit interconnect |
Jan. 24, 2006 |
| 6986914 |
Metal nitride deposition by ALD with reduction pulse |
Jan. 17, 2006 |
| 6987321 |
Copper diffusion deterrent interface |
Jan. 17, 2006 |
| 6984580 |
Dual damascene pattern liner |
Jan. 10, 2006 |
| 6984581 |
Structural reinforcement of highly porous low k dielectric films by ILD posts |
Jan. 10, 2006 |
| 6982200 |
Semiconductor device manufacturing method |
Jan. 3, 2006 |
| 6982227 |
Single and multilevel rework |
Jan. 3, 2006 |
| 6979649 |
Fabrication method of semiconductor integrated circuit device |
Dec. 27, 2005 |
| 6977229 |
Manufacturing method for semiconductor devices |
Dec. 20, 2005 |
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