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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7176126 |
Method of fabricating dual damascene interconnection |
Feb. 13, 2007 |
| 7176123 |
Method for manufacturing metal line of semiconductor device |
Feb. 13, 2007 |
| 7169701 |
Dual damascene trench formation to avoid low-K dielectric damage |
Jan. 30, 2007 |
| 7160799 |
Define via in dual damascene process |
Jan. 9, 2007 |
| 7148157 |
Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon |
Dec. 12, 2006 |
| 7148156 |
Removable amorphous carbon CMP stop |
Dec. 12, 2006 |
| 7129164 |
Method for forming a multi-layer low-K dual damascene |
Oct. 31, 2006 |
| 7119442 |
Semiconductor device |
Oct. 10, 2006 |
| 7119009 |
Semiconductor device with dual damascene wiring |
Oct. 10, 2006 |
| 7119006 |
Via formation for damascene metal conductors in an integrated circuit |
Oct. 10, 2006 |
| 7112528 |
Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
Sep. 26, 2006 |
| 7074708 |
Method of decreasing the k value in sioc layer deposited by chemical vapor deposition |
Jul. 11, 2006 |
| 7074721 |
Method for forming thick copper self-aligned dual damascene |
Jul. 11, 2006 |
| 7071100 |
Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process |
Jul. 4, 2006 |
| 7071112 |
BARC shaping for improved fabrication of dual damascene integrated circuit features |
Jul. 4, 2006 |
| 7071532 |
Adjustable self-aligned air gap dielectric for low capacitance wiring |
Jul. 4, 2006 |
| 7071562 |
Interconnects with improved barrier layer adhesion |
Jul. 4, 2006 |
| 7067419 |
Mask layer and dual damascene interconnect structure in a semiconductor device |
Jun. 27, 2006 |
| 7067426 |
Semiconductor processing methods |
Jun. 27, 2006 |
| 7067919 |
Semiconductor device |
Jun. 27, 2006 |
| 7064059 |
Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer |
Jun. 20, 2006 |
| 7064061 |
Process for fabricating interconnect networks |
Jun. 20, 2006 |
| 7060323 |
Method of forming interlayer insulating film |
Jun. 13, 2006 |
| 7060555 |
Semiconductor device and method of manufacturing the same |
Jun. 13, 2006 |
| 7060605 |
Methods for making dual-damascene dielectric structures |
Jun. 13, 2006 |
| 7060635 |
Method of manufacturing semiconductor device and method of forming pattern |
Jun. 13, 2006 |
| 7057286 |
Semiconductor device and method of manufacturing the same |
Jun. 6, 2006 |
| 7057287 |
Dual damascene integration of ultra low dielectric constant porous materials |
Jun. 6, 2006 |
| 7057289 |
Etch stop in damascene interconnect structure and method of making |
Jun. 6, 2006 |
| 7052621 |
Bilayered metal hardmasks for use in Dual Damascene etch schemes |
May. 30, 2006 |
| 7052990 |
Sealed pores in low-k material damascene conductive structures |
May. 30, 2006 |
| 7053487 |
Semiconductor device |
May. 30, 2006 |
| 7049204 |
High density metal capacitor using via etch stopping layer as field dielectric in dual-damascence interconnect process |
May. 23, 2006 |
| 7049221 |
Method for manufacturing a semiconductor device having a multilayer interconnection structure |
May. 23, 2006 |
| 7049228 |
Method for introducing structures which have different dimensions into a substrate |
May. 23, 2006 |
| 7049249 |
Method of improving stability in low k barrier layers |
May. 23, 2006 |
| 7049702 |
Damascene structure at semiconductor substrate level |
May. 23, 2006 |
| 7045452 |
Circuit structures and methods of forming circuit structures with minimal dielectric constant layers |
May. 16, 2006 |
| 7045898 |
Semiconductor device and manufacturing method thereof |
May. 16, 2006 |
| 7042091 |
Fluorinated hard mask for micropatterning of polymers |
May. 9, 2006 |
| 7042093 |
Semiconductor device using metal nitride as insulating film |
May. 9, 2006 |
| 7041230 |
Method for selectively etching organosilicate glass with respect to a doped silicon carbide |
May. 9, 2006 |
| 7041592 |
Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process |
May. 9, 2006 |
| 7037822 |
Method of forming metal line in semiconductor device |
May. 2, 2006 |
| 7037835 |
Interconnections having double capping layer and method for forming the same |
May. 2, 2006 |
| 7037841 |
Dual damascene interconnecting line structure and fabrication method thereof |
May. 2, 2006 |
| 7038317 |
Semiconductor device and method of manufacturing same |
May. 2, 2006 |
| 7033925 |
Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure |
Apr. 25, 2006 |
| 7033944 |
Dual damascene process |
Apr. 25, 2006 |
| 7034400 |
Dual damascene interconnect structure using low stress fluorosilicate insulator with copper conductors |
Apr. 25, 2006 |
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