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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.


Patents under this class:

Patent Number Title Of Patent Date Issued
6417092 Low dielectric constant etch stop films Jul. 9, 2002
6417094 Dual-damascene interconnect structures and methods of fabricating same Jul. 9, 2002
6417096 Method for avoiding photo residue in dual damascene with acid treatment Jul. 9, 2002
6417098 Enhanced surface modification of low K carbon-doped oxide Jul. 9, 2002
6417112 Post etch cleaning composition and process for dual damascene system Jul. 9, 2002
6414392 Integrated circuit contact Jul. 2, 2002
6413583 Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound Jul. 2, 2002
6413815 Method of forming a MIM capacitor Jul. 2, 2002
6413856 Method of fabricating dual damascene structure Jul. 2, 2002
6410386 Method for forming a metal capacitor in a damascene process Jun. 25, 2002
6410425 Integrated circuit with stop layer and method of manufacturing the same Jun. 25, 2002
6410426 Damascene cap layer process for integrated circuit interconnects Jun. 25, 2002
6410437 Method for etching dual damascene structures in organosilicate glass Jun. 25, 2002
6410453 Method of processing a substrate Jun. 25, 2002
6406992 Fabrication method for a dual damascene structure Jun. 18, 2002
6406995 Pattern-sensitive deposition for damascene processing Jun. 18, 2002
6407011 Low dielectric constant insulating films with laminated carbon-containing silicon oxide and organic layers Jun. 18, 2002
6407453 Semiconductor device and method of manufacturing the same Jun. 18, 2002
6407455 Local interconnect using spacer-masked contact etch Jun. 18, 2002
6403424 Method for forming self-aligned mask read only memory by dual damascene trenches Jun. 11, 2002
6403461 Method to reduce capacitance between metal lines Jun. 11, 2002
6403470 Method for fabricating a dual damascene structure Jun. 11, 2002
6403471 Method of forming a dual damascene structure including smoothing the top part of a via Jun. 11, 2002
6403491 Etch method using a dielectric etch chamber with expanded process window Jun. 11, 2002
6399424 Method of manufacturing contact structure Jun. 4, 2002
6399477 Semiconductor devices and methods for manufacturing semiconductor devices Jun. 4, 2002
6399478 Method of making a dual damascene structure with modified insulation Jun. 4, 2002
6399483 Method for improving faceting effect in dual damascene process Jun. 4, 2002
6399495 Copper interconnections for metal-insulator-metal capacitor in mixed mode signal process Jun. 4, 2002
6399511 Plasma etch process in a single inter-level dielectric etch Jun. 4, 2002
6399512 Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer Jun. 4, 2002
6400023 Integration of low-k SiOF for damascene structure Jun. 4, 2002
6395627 Semiconductor device a burried wiring structure and process for fabricating the same May. 28, 2002
6395632 Etch stop in damascene interconnect structure and method of making May. 28, 2002
6391472 Fill material for dual damascene processes May. 21, 2002
6391757 Dual damascene process May. 21, 2002
6391761 Method to form dual damascene structures using a linear passivation May. 21, 2002
6391766 Method of making a slot via filled dual damascene structure with middle stop layer May. 21, 2002
6391785 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes May. 21, 2002
6387770 Thin-film capacitors and methods for forming the same May. 14, 2002
6387821 Method of manufacturing a semiconductor device May. 14, 2002
6387824 Method for forming porous forming film wiring structure May. 14, 2002
6387859 Method and cleaner composition for stripping copper containing residue layers May. 14, 2002
6384480 Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits May. 7, 2002
6384484 Semiconductor device May. 7, 2002
6383907 Process for fabricating a semiconductor device May. 7, 2002
6383912 Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics May. 7, 2002
6383913 Method for improving surface wettability of low k material May. 7, 2002
6383916 Top layers of metal for high performance IC's May. 7, 2002
6383919 Method of making a dual damascene structure without middle stop layer May. 7, 2002



 
 
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