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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6451683 |
Damascene structure and method of making |
Sep. 17, 2002 |
| 6451688 |
Method for manufacturing a semiconductor device |
Sep. 17, 2002 |
| 6448132 |
Semiconductor device having a lower electrode aperture that is larger than the photolithography resolution of the capacitor pattern |
Sep. 10, 2002 |
| 6448176 |
Dual damascene processing for semiconductor chip interconnects |
Sep. 10, 2002 |
| 6448177 |
Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure |
Sep. 10, 2002 |
| 6448185 |
Method for making a semiconductor device that has a dual damascene interconnect |
Sep. 10, 2002 |
| 6448187 |
Method of improving moisture resistance of low dielectric constant films |
Sep. 10, 2002 |
| 6448652 |
Interconnect structure with a dielectric layer conforming to the perimeter of a wiring layer |
Sep. 10, 2002 |
| 6444557 |
Method of forming a damascene structure using a sacrificial conductive layer |
Sep. 3, 2002 |
| 6444570 |
Method of manufacturing a multi-layered wiring structure for interconnecting semiconductor devices by patterning resist and antireflective films to define wiring grooves |
Sep. 3, 2002 |
| 6444573 |
Method of making a slot via filled dual damascene structure with a middle stop layer |
Sep. 3, 2002 |
| 6444586 |
Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher |
Sep. 3, 2002 |
| 6445073 |
Damascene metallization process and structure |
Sep. 3, 2002 |
| 6440833 |
Method of protecting a copper pad structure during a fuse opening procedure |
Aug. 27, 2002 |
| 6440838 |
Dual damascene structure employing laminated intermediate etch stop layer |
Aug. 27, 2002 |
| 6440842 |
Method of forming a dual damascene structure by patterning a sacrificial layer to define the plug portions of the structure |
Aug. 27, 2002 |
| 6440847 |
Method for forming a via and interconnect in dual damascene |
Aug. 27, 2002 |
| 6440853 |
Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration |
Aug. 27, 2002 |
| 6440861 |
Method of forming dual damascene structure |
Aug. 27, 2002 |
| 6440863 |
Plasma etch method for forming patterned oxygen containing plasma etchable layer |
Aug. 27, 2002 |
| 6440878 |
Method to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon using a silicon carbide adhesion promoter layer |
Aug. 27, 2002 |
| 6441489 |
Semiconductor device with tantalum nitride barrier film |
Aug. 27, 2002 |
| 6441490 |
Low dielectric constant stop layer for integrated circuit interconnects |
Aug. 27, 2002 |
| 6437441 |
Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure |
Aug. 20, 2002 |
| 6436810 |
Bi-layer resist process for dual damascene |
Aug. 20, 2002 |
| 6436817 |
Method for manufacturing a copper interconnection with an aluminum oxide-conductive layer stack barrier layer in semiconductor memory device |
Aug. 20, 2002 |
| 6436824 |
Low dielectric constant materials for copper damascene |
Aug. 20, 2002 |
| 6432619 |
Method for reducing photolithographic steps in a semiconductor interconnect process |
Aug. 13, 2002 |
| 6432810 |
Method of making dual damascene structure |
Aug. 13, 2002 |
| 6432814 |
Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions |
Aug. 13, 2002 |
| 6433381 |
Semiconductor device and method of manufacturing the same |
Aug. 13, 2002 |
| 6433428 |
Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same |
Aug. 13, 2002 |
| 6433432 |
Semiconductor device having fluorined insulating film and reduced fluorine at interconnection interfaces and method of manufacturing the same |
Aug. 13, 2002 |
| 6429105 |
Method of manufacturing semiconductor device |
Aug. 6, 2002 |
| 6429115 |
Method of manufacturing multilevel interconnects including performing a surface treatment to form a hydrophilic surface layer |
Aug. 6, 2002 |
| 6429116 |
Method of fabricating a slot dual damascene structure without middle stop layer |
Aug. 6, 2002 |
| 6429117 |
Method to create copper traps by modifying treatment on the dielectrics surface |
Aug. 6, 2002 |
| 6429119 |
Dual damascene process to reduce etch barrier thickness |
Aug. 6, 2002 |
| 6429121 |
Method of fabricating dual damascene with silicon carbide via mask/ARC |
Aug. 6, 2002 |
| 6429122 |
Non metallic barrier formations for copper damascene type interconnects |
Aug. 6, 2002 |
| 6429129 |
Method of using silicon rich carbide as a barrier material for fluorinated materials |
Aug. 6, 2002 |
| 6426249 |
Buried metal dual damascene plate capacitor |
Jul. 30, 2002 |
| 6426298 |
Method of patterning a dual damascene |
Jul. 30, 2002 |
| 6426558 |
Metallurgy for semiconductor devices |
Jul. 30, 2002 |
| 6424039 |
Dual damascene process using sacrificial spin-on materials |
Jul. 23, 2002 |
| 6424042 |
Semiconductor device and manufacturing method thereof |
Jul. 23, 2002 |
| 6424044 |
Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization |
Jul. 23, 2002 |
| 6420257 |
Process for forming trenches and contacts during the formation of a semiconductor memory device |
Jul. 16, 2002 |
| 6420261 |
Semiconductor device manufacturing method |
Jul. 16, 2002 |
| 6417087 |
Process for forming a dual damascene bond pad structure over active circuitry |
Jul. 9, 2002 |
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