| |
 |
|
Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7507660 |
Deposition processes for tungsten-containing barrier layers |
Mar. 24, 2009 |
| 7504333 |
Method of forming bit line of semiconductor device |
Mar. 17, 2009 |
| 7501353 |
Method of formation of a damascene structure utilizing a protective film |
Mar. 10, 2009 |
| 7501340 |
Methods of forming interconnection lines in semiconductor devices |
Mar. 10, 2009 |
| 7491640 |
Method of manufacturing semiconductor device |
Feb. 17, 2009 |
| 7491639 |
Method of manufacturing a semiconductor device and semiconductor obtained by means of such a method |
Feb. 17, 2009 |
| 7488682 |
High-density 3-dimensional resistors |
Feb. 10, 2009 |
| 7482694 |
Semiconductor device and its manufacturing method |
Jan. 27, 2009 |
| 7482262 |
Method of manufacturing semiconductor device |
Jan. 27, 2009 |
| 7476605 |
Method of manufacturing semiconductor device |
Jan. 13, 2009 |
| 7473999 |
Semiconductor chip and process for forming the same |
Jan. 6, 2009 |
| 7470613 |
Dual damascene multi-level metallization |
Dec. 30, 2008 |
| 7470612 |
Method of forming metal wiring layer of semiconductor device |
Dec. 30, 2008 |
| 7466027 |
Interconnect structures with surfaces roughness improving liner and methods for fabricating the same |
Dec. 16, 2008 |
| 7465652 |
Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device |
Dec. 16, 2008 |
| 7459389 |
Method of forming a semiconductor device having air gaps and the structure so formed |
Dec. 2, 2008 |
| 7452807 |
Method of forming a metal wiring in a semiconductor device |
Nov. 18, 2008 |
| 7452806 |
Method of forming inductor in semiconductor device |
Nov. 18, 2008 |
| 7449407 |
Air gap for dual damascene applications |
Nov. 11, 2008 |
| 7446057 |
Fabrication method |
Nov. 4, 2008 |
| 7439185 |
Method for fabricating semiconductor device and semiconductor device |
Oct. 21, 2008 |
| 7439171 |
Method for manufacturing electronic device |
Oct. 21, 2008 |
| 7435686 |
Semiconductor processing using energized hydrogen gas and in combination with wet cleaning |
Oct. 14, 2008 |
| 7435685 |
Method of forming a low-K dual damascene interconnect structure |
Oct. 14, 2008 |
| 7435679 |
Alloyed underlayer for microelectronic interconnects |
Oct. 14, 2008 |
| 7432191 |
Method of forming a dual damascene structure utilizing a developable anti-reflective coating |
Oct. 7, 2008 |
| 7425502 |
Minimizing resist poisoning in the manufacture of semiconductor devices |
Sep. 16, 2008 |
| 7422981 |
Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole |
Sep. 9, 2008 |
| 7419847 |
Method for forming metal interconnection of semiconductor device |
Sep. 2, 2008 |
| 7416992 |
Method of patterning a low-k dielectric using a hard mask |
Aug. 26, 2008 |
| 7416973 |
Method of increasing the etch selectivity in a contact structure of semiconductor devices |
Aug. 26, 2008 |
| 7410895 |
Methods for forming interconnect structures |
Aug. 12, 2008 |
| 7405153 |
Method for direct electroplating of copper onto a non-copper plateable layer |
Jul. 29, 2008 |
| 7402514 |
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer |
Jul. 22, 2008 |
| 7399700 |
Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating |
Jul. 15, 2008 |
| 7396761 |
Semiconductor device and method of manufacturing the same |
Jul. 8, 2008 |
| 7387961 |
Dual damascene with via liner |
Jun. 17, 2008 |
| 7378350 |
Formation of low resistance via contacts in interconnect structures |
May. 27, 2008 |
| 7378343 |
Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content |
May. 27, 2008 |
| 7375030 |
Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity |
May. 20, 2008 |
| 7375028 |
Method for manufacturing a semiconductor device |
May. 20, 2008 |
| 7375004 |
Method of making an isolation trench and resulting isolation trench |
May. 20, 2008 |
| 7372156 |
Method to fabricate aligned dual damascene openings |
May. 13, 2008 |
| 7372154 |
Semiconductor device |
May. 13, 2008 |
| 7361992 |
Semiconductor device including interconnects formed by damascene process and manufacturing method thereof |
Apr. 22, 2008 |
| 7361589 |
Copper interconnect systems which use conductive, metal-based cap layers |
Apr. 22, 2008 |
| 7358182 |
Method of forming an interconnect structure |
Apr. 15, 2008 |
| 7354859 |
Method of manufacturing semiconductor device |
Apr. 8, 2008 |
| 7354856 |
Method for forming dual damascene structures with tapered via portions and improved performance |
Apr. 8, 2008 |
| 7352064 |
Multiple layer resist scheme implementing etch recipe particular to each layer |
Apr. 1, 2008 |
|
|
|
