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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6518166 |
Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer |
Feb. 11, 2003 |
| 6518171 |
Dual damascene process using a low k interlayer for forming vias and trenches |
Feb. 11, 2003 |
| 6518174 |
Combined resist strip and barrier etch process for dual damascene structures |
Feb. 11, 2003 |
| 6518191 |
Method for etching organic film, method for fabricating semiconductor device and pattern formation method |
Feb. 11, 2003 |
| 6518591 |
Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit |
Feb. 11, 2003 |
| 6518646 |
Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
Feb. 11, 2003 |
| 6514671 |
Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
Feb. 4, 2003 |
| 6514844 |
Sidewall treatment for low dielectric constant (low K) materials by ion implantation |
Feb. 4, 2003 |
| 6514850 |
Interface with dielectric layer and method of making |
Feb. 4, 2003 |
| 6514852 |
Semiconductor device and method of manufacturing the same |
Feb. 4, 2003 |
| 6514856 |
Method for forming multi-layered interconnect structure |
Feb. 4, 2003 |
| 6514857 |
Damascene structure fabricated using a layer of silicon-based photoresist material |
Feb. 4, 2003 |
| 6514860 |
Integration of organic fill for dual damascene process |
Feb. 4, 2003 |
| 6514878 |
Method of fabricating a semiconductor device having a multilayered interconnection structure |
Feb. 4, 2003 |
| 6512260 |
Metal capacitor in damascene structures |
Jan. 28, 2003 |
| 6511903 |
Method of depositing a low k dielectric with organo silane |
Jan. 28, 2003 |
| 6511908 |
Method of manufacturing a dual damascene structure using boron nitride as trench etching stop film |
Jan. 28, 2003 |
| 6511909 |
Method of depositing a low K dielectric with organo silane |
Jan. 28, 2003 |
| 6511916 |
Method for removing the photoresist layer in the damascene process |
Jan. 28, 2003 |
| 6511920 |
Optical marker layer for etch endpoint determination |
Jan. 28, 2003 |
| 6511922 |
Methods and apparatus for producing stable low k FSG film for HDP-CVD |
Jan. 28, 2003 |
| 6509258 |
Etch stop in damascene interconnect structure and method of making |
Jan. 21, 2003 |
| 6509259 |
Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices |
Jan. 21, 2003 |
| 6509267 |
Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
Jan. 21, 2003 |
| 6506680 |
Method of forming connections with low dielectric insulating layers |
Jan. 14, 2003 |
| 6506692 |
Method of making a semiconductor device using a silicon carbide hard mask |
Jan. 14, 2003 |
| 6503818 |
Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material |
Jan. 7, 2003 |
| 6503823 |
Method for manufacturing capacitor elements on a semiconductor substrate |
Jan. 7, 2003 |
| 6503830 |
Method of manufacturing a semiconductor device |
Jan. 7, 2003 |
| 6504205 |
Metal capacitors with damascene structures |
Jan. 7, 2003 |
| 6500357 |
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene |
Dec. 31, 2002 |
| 6500750 |
Semiconductor device and method of formation |
Dec. 31, 2002 |
| 6500773 |
Method of depositing organosilicate layers |
Dec. 31, 2002 |
| 6498089 |
Semiconductor integrated circuit device with moisture-proof ring and its manufacture method |
Dec. 24, 2002 |
| 6498092 |
Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper |
Dec. 24, 2002 |
| 6498364 |
Capacitor for integration with copper damascene processes |
Dec. 24, 2002 |
| 6498385 |
Post-fuse blow corrosion prevention structure for copper fuses |
Dec. 24, 2002 |
| 6498399 |
Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits |
Dec. 24, 2002 |
| 6495442 |
Post passivation interconnection schemes on top of the IC chips |
Dec. 17, 2002 |
| 6495448 |
Dual damascene process |
Dec. 17, 2002 |
| 6495451 |
Method of forming interconnect |
Dec. 17, 2002 |
| 6495452 |
Method to reduce capacitance for copper interconnect structures |
Dec. 17, 2002 |
| 6495478 |
Reduction of shrinkage of poly(arylene ether) for low-K IMD |
Dec. 17, 2002 |
| 6495877 |
Metal capacitors with damascene structures and method for forming the same |
Dec. 17, 2002 |
| 6492263 |
Dual damascene process which prevents diffusion of metals and improves trench-to-via alignment |
Dec. 10, 2002 |
| 6492270 |
Method for forming copper dual damascene |
Dec. 10, 2002 |
| 6492734 |
Semiconductor device including damascene wiring and a manufacturing method thereof |
Dec. 10, 2002 |
| 6488509 |
Plug filling for dual-damascene process |
Dec. 3, 2002 |
| 6489083 |
Selective sizing of features to compensate for resist thickness variations in semiconductor devices |
Dec. 3, 2002 |
| 6489201 |
Method for manufacturing a semiconductor device |
Dec. 3, 2002 |
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