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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6566264 |
Method for forming an opening in a semiconductor device substrate |
May. 20, 2003 |
| 6562416 |
Method of forming low resistance vias |
May. 13, 2003 |
| 6562690 |
Plasma processes for depositing low dielectric constant films |
May. 13, 2003 |
| 6562725 |
Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers |
May. 13, 2003 |
| 6558756 |
Method of forming interlayer insulating film |
May. 6, 2003 |
| 6559049 |
All dual damascene oxide etch process steps in one confined plasma chamber |
May. 6, 2003 |
| 6559545 |
Semiconductor devices and methods for manufacturing semiconductor devices |
May. 6, 2003 |
| 6554002 |
Method for removing etching residues |
Apr. 29, 2003 |
| 6555461 |
Method of forming low resistance barrier on low k interconnect |
Apr. 29, 2003 |
| 6555464 |
Semiconductor device and method of manufacturing the same |
Apr. 29, 2003 |
| 6555467 |
Method of making air gaps copper interconnect |
Apr. 29, 2003 |
| 6555468 |
Method for forming trench including a first and a second layer of photoresist |
Apr. 29, 2003 |
| 6555479 |
Method for forming openings for conductive interconnects |
Apr. 29, 2003 |
| 6551915 |
Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure |
Apr. 22, 2003 |
| 6551919 |
Method for forming a dual inlaid copper interconnect structure |
Apr. 22, 2003 |
| 6551924 |
Post metalization chem-mech polishing dielectric etch |
Apr. 22, 2003 |
| 6551932 |
Method for forming metal line in a semiconductor device |
Apr. 22, 2003 |
| 6548396 |
Method of producing an interconnect structure for an integrated circuit |
Apr. 15, 2003 |
| 6548400 |
Method of fabricating interlevel connectors using only one photomask step |
Apr. 15, 2003 |
| 6548401 |
Semiconductor processing methods, and semiconductor constructions |
Apr. 15, 2003 |
| 6548900 |
Semiconductor device and fabrication method thereof |
Apr. 15, 2003 |
| 6548905 |
Semiconductor device having multi-layer copper line and method of forming the same |
Apr. 15, 2003 |
| 6545753 |
Using scatterometry for etch end points for dual damascene process |
Apr. 8, 2003 |
| 6541842 |
Metal barrier behavior by SiC:H deposition on porous materials |
Apr. 1, 2003 |
| 6540885 |
Profile control of oxide trench features for dual damascene applications |
Apr. 1, 2003 |
| 6541282 |
Plasma processes for depositing low dielectric constant films |
Apr. 1, 2003 |
| 6541374 |
Method of depositing a diffusion barrier for copper interconnection applications |
Apr. 1, 2003 |
| 6541396 |
Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer |
Apr. 1, 2003 |
| 6541397 |
Removable amorphous carbon CMP stop |
Apr. 1, 2003 |
| 6537733 |
Method of depositing low dielectric constant silicon carbide layers |
Mar. 25, 2003 |
| 6537908 |
Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask |
Mar. 25, 2003 |
| 6537929 |
CVD plasma assisted low dielectric constant films |
Mar. 25, 2003 |
| 6534361 |
Method of manufacturing a semiconductor device including metal contact and capacitor |
Mar. 18, 2003 |
| 6534397 |
Pre-treatment of low-k dielectric for prevention of photoresist poisoning |
Mar. 18, 2003 |
| 6534399 |
Dual damascene process using self-assembled monolayer |
Mar. 18, 2003 |
| 6534408 |
Utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
Mar. 18, 2003 |
| 6531390 |
Non-metallic barrier formations for copper damascene type interconnects |
Mar. 11, 2003 |
| 6531398 |
Method of depositing organosillicate layers |
Mar. 11, 2003 |
| 6531403 |
Method of etching an object, method of repairing pattern, nitride pattern and semiconductor device |
Mar. 11, 2003 |
| 6528400 |
Method of manufacturing a semiconductor device |
Mar. 4, 2003 |
| 6528411 |
Semiconductor device and method of its fabrication |
Mar. 4, 2003 |
| 6528426 |
Integrated circuit interconnect and method |
Mar. 4, 2003 |
| 6528428 |
Method of forming dual damascene structure |
Mar. 4, 2003 |
| 6528884 |
Conformal atomic liner layer in an integrated circuit interconnect |
Mar. 4, 2003 |
| 6524947 |
Slotted trench dual inlaid structure and method of forming thereof |
Feb. 25, 2003 |
| 6524962 |
Method for forming dual-damascene interconnect structure |
Feb. 25, 2003 |
| 6525428 |
Graded low-k middle-etch stop layer for dual-inlaid patterning |
Feb. 25, 2003 |
| 6521524 |
Via filled dual damascene structure with middle stop layer and method for making the same |
Feb. 18, 2003 |
| 6521533 |
Method for producing a copper connection |
Feb. 18, 2003 |
| 6521542 |
Method for forming dual damascene structure |
Feb. 18, 2003 |
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