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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6596655 |
Plasma processes for depositing low dielectric constant films |
Jul. 22, 2003 |
| 6597032 |
Metal-insulator-metal (MIM) capacitors |
Jul. 22, 2003 |
| 6594540 |
Misalignment tolerant techniques for dual damascene fabrication |
Jul. 15, 2003 |
| 6593223 |
Method of forming dual damascene structure |
Jul. 15, 2003 |
| 6593225 |
Method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns |
Jul. 15, 2003 |
| 6593232 |
Plasma etch method with enhanced endpoint detection |
Jul. 15, 2003 |
| 6593237 |
Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects |
Jul. 15, 2003 |
| 6593246 |
Process for producing semiconductor device |
Jul. 15, 2003 |
| 6593247 |
Method of depositing low k films using an oxidizing plasma |
Jul. 15, 2003 |
| 6593654 |
Semiconductor device and method for manufacturing same |
Jul. 15, 2003 |
| 6593659 |
Dual damascene structure with carbon containing SiO2 dielectric layers |
Jul. 15, 2003 |
| 6593660 |
Plasma treatment to enhance inorganic dielectric adhesion to copper |
Jul. 15, 2003 |
| 6589711 |
Dual inlaid process using a bilayer resist |
Jul. 8, 2003 |
| 6589862 |
Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices |
Jul. 8, 2003 |
| 6589863 |
Semiconductor device and manufacturing method thereof |
Jul. 8, 2003 |
| 6589874 |
Method for forming electromigration-resistant structures by doping |
Jul. 8, 2003 |
| 6589881 |
Method of forming dual damascene structure |
Jul. 8, 2003 |
| 6589887 |
Forming metal-derived layers by simultaneous deposition and evaporation of metal |
Jul. 8, 2003 |
| 6589888 |
Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers |
Jul. 8, 2003 |
| 6590290 |
Stacked via in copper/polyimide BEOL |
Jul. 8, 2003 |
| 6586334 |
Reducing copper line resistivity by smoothing trench and via sidewalls |
Jul. 1, 2003 |
| 6586842 |
Dual damascene integration scheme for preventing copper contamination of dielectric layer |
Jul. 1, 2003 |
| 6582580 |
Substrate plating apparatus |
Jun. 24, 2003 |
| 6582974 |
Method for forming a dual damascene aperture while employing a peripherally localized intermediate etch stop layer |
Jun. 24, 2003 |
| 6583046 |
Post-treatment of low-k dielectric for prevention of photoresist poisoning |
Jun. 24, 2003 |
| 6583047 |
Method for eliminating reaction between photoresist and OSG |
Jun. 24, 2003 |
| 6583054 |
Method for forming conductive line in semiconductor device |
Jun. 24, 2003 |
| 6579666 |
Methodology to introduce metal and via openings |
Jun. 17, 2003 |
| 6579790 |
Dual damascene manufacturing process |
Jun. 17, 2003 |
| 6579791 |
Method to form dual damascene structure |
Jun. 17, 2003 |
| 6576345 |
Dielectric films with low dielectric constants |
Jun. 10, 2003 |
| 6576550 |
`Via first` dual damascene process for copper metallization |
Jun. 10, 2003 |
| 6576562 |
Manufacturing method of semiconductor device using mask pattern having high etching resistance |
Jun. 10, 2003 |
| 6576982 |
Use of sion for preventing copper contamination of dielectric layer |
Jun. 10, 2003 |
| 6573030 |
Method for depositing an amorphous carbon layer |
Jun. 3, 2003 |
| 6573170 |
Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device |
Jun. 3, 2003 |
| 6573175 |
Dry low k film application for interlevel dielectric and method of cleaning etched features |
Jun. 3, 2003 |
| 6573176 |
Method for forming dual damascene line structure |
Jun. 3, 2003 |
| 6573187 |
Method of forming dual damascene structure |
Jun. 3, 2003 |
| 6573196 |
Method of depositing organosilicate layers |
Jun. 3, 2003 |
| 6573572 |
Damascene structure and method of making |
Jun. 3, 2003 |
| 6573601 |
Integrated circuit contact |
Jun. 3, 2003 |
| 6573607 |
Semiconductor device and manufacturing method thereof |
Jun. 3, 2003 |
| 6569760 |
Method to prevent poison via |
May. 27, 2003 |
| 6569777 |
Plasma etching method to form dual damascene with improved via profile |
May. 27, 2003 |
| 6570257 |
IMD film composition for dual damascene process |
May. 27, 2003 |
| 6566242 |
Dual damascene copper interconnect to a damascene tungsten wiring level |
May. 20, 2003 |
| 6566243 |
Dielectric layer including silicalite crystals and binder and method for producing same for microelectronic circuits |
May. 20, 2003 |
| 6566258 |
Bi-layer etch stop for inter-level via |
May. 20, 2003 |
| 6566260 |
Non-metallic barrier formations for copper damascene type interconnects |
May. 20, 2003 |
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