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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.


Patents under this class:
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Patent Number Title Of Patent Date Issued
6670267 Formation of tungstein-based interconnect using thin physically vapor deposited titanium nitride layer Dec. 30, 2003
6670271 Growing a dual damascene structure using a copper seed layer and a damascene resist structure Dec. 30, 2003
6670278 Method of plasma etching of silicon carbide Dec. 30, 2003
6670709 Semiconductor device and method of manufacturing the same Dec. 30, 2003
6667231 Method of forming barrier films for copper metallization over low dielectric constant insulators in an integrated circuit Dec. 23, 2003
6667530 Semiconductor device and manufacturing method thereof Dec. 23, 2003
6663787 Use of ta/tan for preventing copper contamination of low-k dielectric layers Dec. 16, 2003
6664177 Dielectric ARC scheme to improve photo window in dual damascene process Dec. 16, 2003
6664179 Semiconductor device production method and semiconductor device production apparatus Dec. 16, 2003
6664181 Method for fabricating semiconductor device Dec. 16, 2003
6664182 Method of improving the interlayer adhesion property of low-k layers in a dual damascene process Dec. 16, 2003
6664192 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes Dec. 16, 2003
6660546 Method of etching an object, method of repairing pattern, nitride pattern and semiconductor device Dec. 9, 2003
6660619 Dual damascene metal interconnect structure with dielectric studs Dec. 9, 2003
6660630 Method for forming a tapered dual damascene via portion with improved performance Dec. 9, 2003
6660636 Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating Dec. 9, 2003
6660656 Plasma processes for depositing low dielectric constant films Dec. 9, 2003
6660663 Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds Dec. 9, 2003
6661094 Semiconductor device having a dual damascene interconnect spaced from a support structure Dec. 9, 2003
6656532 Layered hard mask and dielectric materials and methods therefor Dec. 2, 2003
6656830 Dual damascene with silicon carbide middle etch stop layer/ARC Dec. 2, 2003
6656837 Method of eliminating photoresist poisoning in damascene applications Dec. 2, 2003
6656840 Method for forming silicon containing layers on a substrate Dec. 2, 2003
6657284 Graded dielectric layer and method for fabrication thereof Dec. 2, 2003
6657304 Conformal barrier liner in an integrated circuit interconnect Dec. 2, 2003
6657310 Top layers of metal for high performance IC's Dec. 2, 2003
6653223 Dual damascene method employing void forming via filling dielectric layer Nov. 25, 2003
6649495 Manufacturing method of semiconductor device Nov. 18, 2003
6649509 Post passivation metal scheme for high-performance integrated circuit devices Nov. 18, 2003
6649512 Method for improving adhesion of a low k dielectric to a barrier layer Nov. 18, 2003
6649515 Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures Nov. 18, 2003
6649522 Etch stop in damascene interconnect structure and method of making Nov. 18, 2003
6649531 Process for forming a damascene structure Nov. 18, 2003
6645811 Capacitor using high dielectric constant film for semiconductor memory device and fabrication method therefor Nov. 11, 2003
6645851 Method of forming planarized coatings on contact hole patterns of various duty ratios Nov. 11, 2003
6645852 Process for fabricating a semiconductor device having recess portion Nov. 11, 2003
6645853 Interconnects with improved barrier layer adhesion Nov. 11, 2003
6645864 Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning Nov. 11, 2003
6645873 Method for manufacturing a semiconductor device Nov. 11, 2003
6641982 Methodology to introduce metal and via openings Nov. 4, 2003
6642138 Process of making dual damascene structures using a sacrificial polymer Nov. 4, 2003
6642139 Method for forming interconnection structure in an integration circuit Nov. 4, 2003
6642153 Method for avoiding unetched polymer residue in anisotropically etched semiconductor features Nov. 4, 2003
6642563 Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same Nov. 4, 2003
6638853 Method for avoiding photoresist resist residue on semioconductor feature sidewalls Oct. 28, 2003
6638871 Method for forming openings in low dielectric constant material layer Oct. 28, 2003
6639320 Reticle for creating resist-filled vias in a dual damascene process Oct. 28, 2003
6635565 Method of cleaning a dual damascene structure Oct. 21, 2003
6635566 Method of making metallization and contact structures in an integrated circuit Oct. 21, 2003
6635583 Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating Oct. 21, 2003

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