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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6716742 |
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
Apr. 6, 2004 |
| 6716754 |
Methods of forming patterns and molds for semiconductor constructions |
Apr. 6, 2004 |
| 6717265 |
Treatment of low-k dielectric material for CMP |
Apr. 6, 2004 |
| 6713386 |
Method of preventing resist poisoning in dual damascene structures |
Mar. 30, 2004 |
| 6713402 |
Methods for polymer removal following etch-stop layer etch |
Mar. 30, 2004 |
| 6713873 |
Adhesion between dielectric materials |
Mar. 30, 2004 |
| 6709986 |
Method for manufacturing semiconductor memory device by using photoresist pattern exposed with ArF laser beam |
Mar. 23, 2004 |
| 6709990 |
Method for fabrication of a high capacitance interpoly dielectric |
Mar. 23, 2004 |
| 6710450 |
Interconnect structure with precise conductor resistance and method to form same |
Mar. 23, 2004 |
| 6710451 |
Interconnect structure and method for forming the same |
Mar. 23, 2004 |
| 6706611 |
Method for patterning a dual damascene with retrograde implantation |
Mar. 16, 2004 |
| 6706629 |
Barrier-free copper interconnect |
Mar. 16, 2004 |
| 6706637 |
Dual damascene aperture formation method absent intermediate etch stop layer |
Mar. 16, 2004 |
| 6703304 |
Dual damascene process using self-assembled monolayer and spacers |
Mar. 9, 2004 |
| 6703324 |
Mechanically reinforced highly porous low dielectric constant films |
Mar. 9, 2004 |
| 6699396 |
Methods for electroplating large copper interconnects |
Mar. 2, 2004 |
| 6699783 |
Method for controlling conformality with alternating layer deposition |
Mar. 2, 2004 |
| 6699784 |
Method for depositing a low k dielectric film (K>3.5) for hard mask application |
Mar. 2, 2004 |
| 6700202 |
Semiconductor device having reduced oxidation interface |
Mar. 2, 2004 |
| 6696222 |
Dual damascene process using metal hard mask |
Feb. 24, 2004 |
| 6696360 |
Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
Feb. 24, 2004 |
| 6696363 |
Method of and apparatus for substrate pre-treatment |
Feb. 24, 2004 |
| 6692580 |
Method of cleaning a dual damascene structure |
Feb. 17, 2004 |
| 6693028 |
Semiconductor device having multilayer wiring structure and method for manufacturing the same |
Feb. 17, 2004 |
| 6693049 |
Method for filling fine hole |
Feb. 17, 2004 |
| 6689681 |
Semiconductor device and a method of manufacturing the same |
Feb. 10, 2004 |
| 6689684 |
Cu damascene interconnections using barrier/capping layer |
Feb. 10, 2004 |
| 6689693 |
Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
Feb. 10, 2004 |
| 6689695 |
Multi-purpose composite mask for dual damascene patterning |
Feb. 10, 2004 |
| 6690091 |
Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer |
Feb. 10, 2004 |
| 6686270 |
Dual damascene trench depth monitoring |
Feb. 3, 2004 |
| 6686271 |
Protective layers prior to alternating layer deposition |
Feb. 3, 2004 |
| 6686273 |
Method of fabricating copper interconnects with very low-k inter-level insulator |
Feb. 3, 2004 |
| 6686293 |
Method of etching a trench in a silicon-containing dielectric material |
Feb. 3, 2004 |
| 6686662 |
Semiconductor device barrier layer |
Feb. 3, 2004 |
| 6683002 |
Method to create a copper diffusion deterrent interface |
Jan. 27, 2004 |
| 6680247 |
Manufacturing method of a semiconductor device |
Jan. 20, 2004 |
| 6680248 |
Method of forming dual damascene structure |
Jan. 20, 2004 |
| 6680249 |
Si-rich surface layer capped diffusion barriers |
Jan. 20, 2004 |
| 6680252 |
Method for planarizing barc layer in dual damascene process |
Jan. 20, 2004 |
| 6680262 |
Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface |
Jan. 20, 2004 |
| 6680540 |
Semiconductor device having cobalt alloy film with boron |
Jan. 20, 2004 |
| 6680541 |
Semiconductor device and process for producing the same |
Jan. 20, 2004 |
| 6677231 |
Method for increasing adhesion ability of dielectric material in semiconductor |
Jan. 13, 2004 |
| 6677251 |
Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion |
Jan. 13, 2004 |
| 6677635 |
Stacked MIMCap between Cu dual damascene levels |
Jan. 13, 2004 |
| 6677678 |
Damascene structure using a sacrificial conductive layer |
Jan. 13, 2004 |
| 6677680 |
Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials |
Jan. 13, 2004 |
| 6674168 |
Single and multilevel rework |
Jan. 6, 2004 |
| 6669858 |
Integrated low k dielectrics and etch stops |
Dec. 30, 2003 |
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