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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6743711 |
Method for forming dual damascene line structure |
Jun. 1, 2004 |
| 6743712 |
Method of making a semiconductor device by forming a masking layer with a tapered etch profile |
Jun. 1, 2004 |
| 6743713 |
Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC) |
Jun. 1, 2004 |
| 6743718 |
Process for producing barrier film and barrier film thus produced |
Jun. 1, 2004 |
| 6743725 |
High selectivity SiC etch in integrated circuit fabrication |
Jun. 1, 2004 |
| 6743726 |
Method for etching a trench through an anti-reflective coating |
Jun. 1, 2004 |
| 6743730 |
Plasma processing method |
Jun. 1, 2004 |
| 6743737 |
Method of improving moisture resistance of low dielectric constant films |
Jun. 1, 2004 |
| 6744090 |
Damascene capacitor formed in metal interconnection layer |
Jun. 1, 2004 |
| 6740579 |
Method of making a semiconductor device that includes a dual damascene interconnect |
May. 25, 2004 |
| 6740976 |
Semiconductor device including via contact plug with a discontinuous barrier layer |
May. 25, 2004 |
| 6737222 |
Dual damascene process utilizing a bi-layer imaging layer |
May. 18, 2004 |
| 6737310 |
Self-aligned process for a stacked gate RF MOSFET device |
May. 18, 2004 |
| 6737350 |
Method of manufacturing semiconductor device |
May. 18, 2004 |
| 6737357 |
Method for manufacturing a semiconductor device |
May. 18, 2004 |
| 6737744 |
Semiconductor device including porous insulating material and manufacturing method therefor |
May. 18, 2004 |
| 6737747 |
Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
May. 18, 2004 |
| 6733597 |
Method of cleaning a dual damascene structure |
May. 11, 2004 |
| 6734090 |
Method of making an edge seal for a semiconductor device |
May. 11, 2004 |
| 6734094 |
Method of forming an air gap within a structure by exposing an ultraviolet sensitive material to ultraviolet radiation |
May. 11, 2004 |
| 6734096 |
Fine-pitch device lithography using a sacrificial hardmask |
May. 11, 2004 |
| 6734097 |
Liner with poor step coverage to improve contact resistance in W contacts |
May. 11, 2004 |
| 6734102 |
Plasma treatment for copper oxide reduction |
May. 11, 2004 |
| 6734115 |
Plasma processes for depositing low dielectric constant films |
May. 11, 2004 |
| 6734116 |
Damascene method employing multi-layer etch stop layer |
May. 11, 2004 |
| 6734489 |
Semiconductor element and MIM-type capacitor formed in different layers of a semiconductor device |
May. 11, 2004 |
| 6734563 |
Post passivation interconnection schemes on top of the IC chips |
May. 11, 2004 |
| 6730591 |
Method of using silicon rich carbide as a barrier material for fluorinated materials |
May. 4, 2004 |
| 6730593 |
Method of depositing a low K dielectric with organo silane |
May. 4, 2004 |
| 6730601 |
Methods for fabricating a metal-oxide-metal capacitor |
May. 4, 2004 |
| 6731006 |
Doped copper interconnects using laser thermal annealing |
May. 4, 2004 |
| 6727183 |
Prevention of spiking in ultra low dielectric constant material |
Apr. 27, 2004 |
| 6727515 |
Insulation film forming material, insulation film, method for forming the insulation film, and semiconductor device |
Apr. 27, 2004 |
| 6727589 |
Dual damascene flowable oxide insulation structure and metallic barrier |
Apr. 27, 2004 |
| 6723631 |
Fabrication method of semiconductor integrated circuit device |
Apr. 20, 2004 |
| 6723634 |
Method of forming interconnects with improved barrier layer adhesion |
Apr. 20, 2004 |
| 6723635 |
Protection low-k ILD during damascene processing with thin liner |
Apr. 20, 2004 |
| 6723636 |
Methods for forming multiple damascene layers |
Apr. 20, 2004 |
| 6723645 |
Method of forming a metal wiring in a semiconductor device |
Apr. 20, 2004 |
| 6724069 |
Spin-on cap layer, and semiconductor device containing same |
Apr. 20, 2004 |
| 6724085 |
Semiconductor device with reduced resistance plug wire for interconnection |
Apr. 20, 2004 |
| 6720027 |
Cyclical deposition of a variable content titanium silicon nitride layer |
Apr. 13, 2004 |
| 6720247 |
Pre-pattern surface modification for low-k dielectrics using A H2 plasma |
Apr. 13, 2004 |
| 6720248 |
Method of forming metal interconnection layer in semiconductor device |
Apr. 13, 2004 |
| 6720249 |
Protective hardmask for producing interconnect structures |
Apr. 13, 2004 |
| 6720252 |
Method of deep contact fill and planarization for dual damascene structures |
Apr. 13, 2004 |
| 6720255 |
Semiconductor device with silicon-carbon-oxygen dielectric having improved metal barrier adhesion and method of forming the device |
Apr. 13, 2004 |
| 6720256 |
Method of dual damascene patterning |
Apr. 13, 2004 |
| 6716302 |
Dielectric etch chamber with expanded process window |
Apr. 6, 2004 |
| 6716741 |
Method of patterning dielectric layer with low dielectric constant |
Apr. 6, 2004 |
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