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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6780761 |
Via-first dual damascene process |
Aug. 24, 2004 |
| 6780778 |
Method for fabricating semiconductor device |
Aug. 24, 2004 |
| 6781235 |
Three-level unitary interconnect structure |
Aug. 24, 2004 |
| 6777171 |
Fluorine-containing layers for damascene structures |
Aug. 17, 2004 |
| 6777323 |
Lamination structure with copper wiring and its manufacture method |
Aug. 17, 2004 |
| 6777332 |
Method for forming wiring structure |
Aug. 17, 2004 |
| 6774020 |
Semiconductor device and method of manufacturing the same |
Aug. 10, 2004 |
| 6774028 |
Method of forming wiring structure by using photo resist having optimum development rate |
Aug. 10, 2004 |
| 6774031 |
Method of forming dual-damascene structure |
Aug. 10, 2004 |
| 6774037 |
Method integrating polymeric interlayer dielectric in integrated circuits |
Aug. 10, 2004 |
| 6774053 |
Method and structure for low-k dielectric constant applications |
Aug. 10, 2004 |
| 6770556 |
Method of depositing a low dielectric with organo silane |
Aug. 3, 2004 |
| 6770975 |
Integrated circuits with multiple low dielectric-constant inter-metal dielectrics |
Aug. 3, 2004 |
| 6767788 |
Semiconductor device having a metal insulator metal capacitor |
Jul. 27, 2004 |
| 6767825 |
Etching process for forming damascene structure of the semiconductor |
Jul. 27, 2004 |
| 6767826 |
Method of manufacturing semiconductor device |
Jul. 27, 2004 |
| 6767827 |
Method for forming dual inlaid structures for IC interconnections |
Jul. 27, 2004 |
| 6767833 |
Method for damascene reworking |
Jul. 27, 2004 |
| 6764810 |
Method for dual-damascene formation using a via plug |
Jul. 20, 2004 |
| 6764939 |
Semiconductor device and method of manufacturing the same |
Jul. 20, 2004 |
| 6764944 |
Method for forming metal wire interconnection in semiconductor devices using dual damascene process |
Jul. 20, 2004 |
| 6764950 |
Fabrication method for semiconductor integrated circuit device |
Jul. 20, 2004 |
| 6764958 |
Method of depositing dielectric films |
Jul. 20, 2004 |
| 6765255 |
Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof |
Jul. 20, 2004 |
| 6765283 |
Semiconductor device with multi-layer interlayer dielectric film |
Jul. 20, 2004 |
| 6765294 |
Semiconductor device including dual-damascene structure and method for manufacturing the same |
Jul. 20, 2004 |
| 6762076 |
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
Jul. 13, 2004 |
| 6762087 |
Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor |
Jul. 13, 2004 |
| 6762109 |
Method of manufacturing semiconductor device with reduced number of process steps for capacitor formation |
Jul. 13, 2004 |
| 6762115 |
Chip structure and process for forming the same |
Jul. 13, 2004 |
| 6762127 |
Etch process for dielectric materials comprising oxidized organo silane materials |
Jul. 13, 2004 |
| 6762500 |
Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
Jul. 13, 2004 |
| 6759703 |
Capacitor and a manufacturing process therefor |
Jul. 6, 2004 |
| 6760901 |
Trough adjusted optical proximity correction for vias |
Jul. 6, 2004 |
| 6758223 |
Plasma RIE polymer removal |
Jul. 6, 2004 |
| 6759322 |
Method for forming wiring structure |
Jul. 6, 2004 |
| 6759325 |
Sealing porous structures |
Jul. 6, 2004 |
| 6759327 |
Method of depositing low k barrier layers |
Jul. 6, 2004 |
| 6756295 |
Chip structure and process for forming the same |
Jun. 29, 2004 |
| 6756297 |
Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer |
Jun. 29, 2004 |
| 6756299 |
Process for fabricating a semiconductor device |
Jun. 29, 2004 |
| 6756300 |
Method for forming dual damascene interconnect structure |
Jun. 29, 2004 |
| 6756321 |
Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant |
Jun. 29, 2004 |
| 6756672 |
Use of sic for preventing copper contamination of low-k dielectric layers |
Jun. 29, 2004 |
| 6753258 |
Integration scheme for dual damascene structure |
Jun. 22, 2004 |
| 6753269 |
Method for low k dielectric deposition |
Jun. 22, 2004 |
| 6749765 |
Aperture fill |
Jun. 15, 2004 |
| 6750141 |
Silicon carbide cap layers for low dielectric constant silicon oxide layers |
Jun. 15, 2004 |
| 6746947 |
Post-fuse blow corrosion prevention structure for copper fuses |
Jun. 8, 2004 |
| 6743711 |
Method for forming dual damascene line structure |
Jun. 1, 2004 |
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