Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo) > Patents

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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.

Patents under this class:

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Patent Number	Title Of Patent	Date Issued
6806111	Semiconductor component and method of manufacture	Oct. 19, 2004
6806195	Manufacturing method of semiconductor IC device	Oct. 19, 2004
6806203	Method of forming a dual damascene structure using an amorphous silicon hard mask	Oct. 19, 2004
6806207	Method of depositing low K films	Oct. 19, 2004
6803304	Methods for producing electrode and semiconductor device	Oct. 12, 2004
6803305	Method for forming a via in a damascene process	Oct. 12, 2004
6803306	High density metal capacitor using via etch stopping layer as field dielectric in dual-damascence interconnect process	Oct. 12, 2004
6803308	Method of forming a dual damascene pattern in a semiconductor device	Oct. 12, 2004
6803309	Method for depositing an adhesion/barrier layer to improve adhesion and contact resistance	Oct. 12, 2004
6800548	Method to avoid via poisoning in dual damascene process	Oct. 5, 2004
6800549	Method of fabricating semiconductor device including forming contact hole with anisotropic and isotropic etching and forming discontinuous barrier layer	Oct. 5, 2004
6800550	Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon	Oct. 5, 2004
6800551	Chemical amplification type photoresist composition, method for producing a semiconductor device using the composition, and semiconductor substrate	Oct. 5, 2004
6800552	Deposition of transition metal carbides	Oct. 5, 2004
6800571	CVD plasma assisted low dielectric constant films	Oct. 5, 2004
6797605	Method to improve adhesion of dielectric films in damascene interconnects	Sep. 28, 2004
6797630	Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach	Sep. 28, 2004
6797633	In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning	Sep. 28, 2004
6797639	Dielectric etch chamber with expanded process window	Sep. 28, 2004
6797646	Method of nitrogen doping of fluorinated silicate glass (FSG) while removing the photoresist layer	Sep. 28, 2004
6798043	Structure and method for isolating porous low-k dielectric films	Sep. 28, 2004
6798073	Chip structure and process for forming the same	Sep. 28, 2004
6793835	System level in-situ integrated dielectric etch process particularly useful for copper dual damascene	Sep. 21, 2004
6794244	Semiconductor device and method of manufacturing the same	Sep. 21, 2004
6794262	MIM capacitor structures and fabrication methods in dual-damascene structures	Sep. 21, 2004
6794283	Semiconductor device and fabrication method thereof	Sep. 21, 2004
6794286	Process for fabricating a metal wiring and metal contact in a semicondutor device	Sep. 21, 2004
6794292	Extrusion-free wet cleaning process for copper-dual damascene structures	Sep. 21, 2004
6794293	Trench etch process for low-k dielectrics	Sep. 21, 2004
6794755	Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement	Sep. 21, 2004
6790723	Semiconductor device and method of manufacturing the same	Sep. 14, 2004
6790766	Method of fabricating semiconductor device having low dielectric constant insulator film	Sep. 14, 2004
6790770	Method for preventing photoresist poisoning	Sep. 14, 2004
6790772	Dual damascene processing method using silicon rich oxide layer thereof and its structure	Sep. 14, 2004
6790780	Fabrication of 3-D capacitor with dual damascene process	Sep. 14, 2004
6790784	Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure	Sep. 14, 2004
6790788	Method of improving stability in low k barrier layers	Sep. 14, 2004
6787446	Fabrication method of semiconductor integrated circuit device	Sep. 7, 2004
6787447	Semiconductor processing methods of forming integrated circuitry	Sep. 7, 2004
6787448	Methods for forming metal interconnections for semiconductor devices using a buffer layer on a trench sidewall	Sep. 7, 2004
6787452	Use of amorphous carbon as a removable ARC material for dual damascene fabrication	Sep. 7, 2004
6787454	Method of manufacturing semiconductor device having dual damascene structure	Sep. 7, 2004
6787472	Utilization of disappearing silicon hard mask for fabrication of semiconductor structures	Sep. 7, 2004
6787875	Self-aligned vias in an integrated circuit structure	Sep. 7, 2004
6787907	Semiconductor device with dual damascene wiring	Sep. 7, 2004
6787914	Tungsten-based interconnect that utilizes thin titanium nitride layer	Sep. 7, 2004
6783862	Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures	Aug. 31, 2004
6784109	Method for fabricating semiconductor devices including wiring forming with a porous low-k film and copper	Aug. 31, 2004
6784119	Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition	Aug. 31, 2004
6784478	Junction capacitor structure and fabrication method therefor in a dual damascene process	Aug. 31, 2004