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Class Information
Number: 257/E21.579
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo) > For "dual damascene" type structures (epo)
Description: This subclass is indented under subclass E21.577. This subclass is substantially the same in scope as ECLA classification H01L21/768B2D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7432191 |
Method of forming a dual damascene structure utilizing a developable anti-reflective coating |
Oct. 7, 2008 |
| 7425502 |
Minimizing resist poisoning in the manufacture of semiconductor devices |
Sep. 16, 2008 |
| 7422981 |
Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole |
Sep. 9, 2008 |
| 7419847 |
Method for forming metal interconnection of semiconductor device |
Sep. 2, 2008 |
| 7416992 |
Method of patterning a low-k dielectric using a hard mask |
Aug. 26, 2008 |
| 7416973 |
Method of increasing the etch selectivity in a contact structure of semiconductor devices |
Aug. 26, 2008 |
| 7410895 |
Methods for forming interconnect structures |
Aug. 12, 2008 |
| 7405153 |
Method for direct electroplating of copper onto a non-copper plateable layer |
Jul. 29, 2008 |
| 7402514 |
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer |
Jul. 22, 2008 |
| 7399700 |
Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating |
Jul. 15, 2008 |
| 7396761 |
Semiconductor device and method of manufacturing the same |
Jul. 8, 2008 |
| 7387961 |
Dual damascene with via liner |
Jun. 17, 2008 |
| 7378350 |
Formation of low resistance via contacts in interconnect structures |
May. 27, 2008 |
| 7378343 |
Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content |
May. 27, 2008 |
| 7375030 |
Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity |
May. 20, 2008 |
| 7375028 |
Method for manufacturing a semiconductor device |
May. 20, 2008 |
| 7375004 |
Method of making an isolation trench and resulting isolation trench |
May. 20, 2008 |
| 7372156 |
Method to fabricate aligned dual damascene openings |
May. 13, 2008 |
| 7372154 |
Semiconductor device |
May. 13, 2008 |
| 7361992 |
Semiconductor device including interconnects formed by damascene process and manufacturing method thereof |
Apr. 22, 2008 |
| 7361589 |
Copper interconnect systems which use conductive, metal-based cap layers |
Apr. 22, 2008 |
| 7358182 |
Method of forming an interconnect structure |
Apr. 15, 2008 |
| 7354859 |
Method of manufacturing semiconductor device |
Apr. 8, 2008 |
| 7354856 |
Method for forming dual damascene structures with tapered via portions and improved performance |
Apr. 8, 2008 |
| 7352064 |
Multiple layer resist scheme implementing etch recipe particular to each layer |
Apr. 1, 2008 |
| 7351635 |
Method of fabricating microelectronic device using super critical fluid |
Apr. 1, 2008 |
| 7348281 |
Method of filling structures for forming via-first dual damascene interconnects |
Mar. 25, 2008 |
| 7344972 |
Photosensitive dielectric layer |
Mar. 18, 2008 |
| 7338895 |
Method for dual damascene integration of ultra low dielectric constant porous materials |
Mar. 4, 2008 |
| 7335991 |
Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus |
Feb. 26, 2008 |
| 7335588 |
Interconnect structure and method of fabrication of same |
Feb. 26, 2008 |
| 7329955 |
Metal-insulator-metal (MIM) capacitor |
Feb. 12, 2008 |
| 7329602 |
Wiring structure for integrated circuit with reduced intralevel capacitance |
Feb. 12, 2008 |
| 7323407 |
Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material |
Jan. 29, 2008 |
| 7319071 |
Methods for forming a metallic damascene structure |
Jan. 15, 2008 |
| 7315082 |
Semiconductor device having integrated circuit contact |
Jan. 1, 2008 |
| 7314823 |
Chemical mechanical polishing composition and process |
Jan. 1, 2008 |
| 7312146 |
Semiconductor device interconnect fabricating techniques |
Dec. 25, 2007 |
| 7309649 |
Method of forming closed air gap interconnects and structures formed thereby |
Dec. 18, 2007 |
| 7307016 |
Method of processing metal surface in dual damascene manufacturing |
Dec. 11, 2007 |
| 7307015 |
Method for forming an interconnection line in a semiconductor device |
Dec. 11, 2007 |
| 7307014 |
Method of forming a via contact structure using a dual damascene process |
Dec. 11, 2007 |
| 7300867 |
Dual damascene interconnect structures having different materials for line and via conductors |
Nov. 27, 2007 |
| 7300825 |
Customizing back end of the line interconnects |
Nov. 27, 2007 |
| 7285490 |
Method for the producing an integrated circuit bar arrangement, in particular comprising a capacitor assembly, in addition to an integrated circuit arrangement |
Oct. 23, 2007 |
| 7285489 |
Dual damascene process for forming a multi-layer low-k dielectric interconnect |
Oct. 23, 2007 |
| 7274104 |
Semiconductor device having an interconnect that increases in impurity concentration as width increases |
Sep. 25, 2007 |
| 7265450 |
Semiconductor device and method for fabricating the same |
Sep. 4, 2007 |
| 7262133 |
Enhancement of copper line reliability using thin ALD tan film to cap the copper line |
Aug. 28, 2007 |
| 7259089 |
Semiconductor device manufacturing method that includes forming a wiring pattern with a mask layer that has a tapered shape |
Aug. 21, 2007 |
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