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Class Information
Number: 257/E21.577
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > By forming via holes (epo)
Description: This subclass is indented under subclass E21.576. This subclass is substantially the same in scope as ECLA classification H01L21/768B2.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7615486 |
Apparatus and method for integrated surface treatment and deposition for copper interconnect |
Nov. 10, 2009 |
| 7615485 |
Method of manufacture of contact plug and interconnection layer of semiconductor device |
Nov. 10, 2009 |
| 7608536 |
Method of manufacturing contact opening |
Oct. 27, 2009 |
| 7605081 |
Sub-lithographic feature patterning using self-aligned self-assembly polymers |
Oct. 20, 2009 |
| 7605014 |
Method of fabricating resistive probe having self-aligned metal shield |
Oct. 20, 2009 |
| 7598169 |
Method to remove beol sacrificial materials and chemical residues by irradiation |
Oct. 6, 2009 |
| 7595267 |
Method of forming contact hole of semiconductor device |
Sep. 29, 2009 |
| 7595236 |
Method for production of semiconductor device having a hole extending through a first insulating film, a second insulating film and a third insulating film |
Sep. 29, 2009 |
| 7592258 |
Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same |
Sep. 22, 2009 |
| 7585758 |
Interconnect layers without electromigration |
Sep. 8, 2009 |
| 7585757 |
Semiconductor device and method of manufacturing the same |
Sep. 8, 2009 |
| 7576002 |
Multi-step barrier deposition method |
Aug. 18, 2009 |
| 7569403 |
Pattern evaluation method, manufacturing method of semiconductor device, correction method of mask pattern and manufacturing method of exposure mask |
Aug. 4, 2009 |
| 7566658 |
Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device |
Jul. 28, 2009 |
| 7566652 |
Electrically inactive via for electromigration reliability improvement |
Jul. 28, 2009 |
| 7563687 |
Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit |
Jul. 21, 2009 |
| 7557304 |
Printed circuit board having closed vias |
Jul. 7, 2009 |
| 7557045 |
Manufacture of semiconductor device with good contact holes |
Jul. 7, 2009 |
| 7557039 |
Method for fabricating contact hole of semiconductor device |
Jul. 7, 2009 |
| 7557025 |
Method of etching a dielectric layer to form a contact hole and a via hole and damascene method |
Jul. 7, 2009 |
| 7553699 |
Method of fabricating microelectronic devices |
Jun. 30, 2009 |
| 7550853 |
Electrical isolation of monolithic circuits using a conductive through-hole in the substrate |
Jun. 23, 2009 |
| 7550822 |
Dual-damascene metal wiring patterns for integrated circuit devices |
Jun. 23, 2009 |
| 7550376 |
Semiconductor device capable of suppressing current concentration in pad and its manufacture method |
Jun. 23, 2009 |
| 7550321 |
Substrate having a functionally gradient coefficient of thermal expansion |
Jun. 23, 2009 |
| 7547628 |
Method for manufacturing capacitor |
Jun. 16, 2009 |
| 7545045 |
Dummy via for reducing proximity effect and method of using the same |
Jun. 9, 2009 |
| 7544623 |
Method for fabricating a contact hole |
Jun. 9, 2009 |
| 7544605 |
Method of making a contact on a backside of a die |
Jun. 9, 2009 |
| 7538028 |
Barrier layer, IC via, and IC line forming methods |
May. 26, 2009 |
| 7538023 |
Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area |
May. 26, 2009 |
| 7534720 |
Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer |
May. 19, 2009 |
| 7534711 |
System and method for direct etching |
May. 19, 2009 |
| 7524758 |
Interconnect structure and method for semiconductor device |
Apr. 28, 2009 |
| 7521347 |
Method for forming contact hole in semiconductor device |
Apr. 21, 2009 |
| 7517799 |
Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer |
Apr. 14, 2009 |
| 7514365 |
Method of fabricating opening and plug |
Apr. 7, 2009 |
| 7510962 |
Method for producing an anisotropic conductive film on a substrate |
Mar. 31, 2009 |
| 7504287 |
Methods for fabricating an integrated circuit |
Mar. 17, 2009 |
| 7501342 |
Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same |
Mar. 10, 2009 |
| 7498677 |
Semiconductor device |
Mar. 3, 2009 |
| 7498254 |
Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
Mar. 3, 2009 |
| 7498253 |
Local interconnection method and structure for use in semiconductor device |
Mar. 3, 2009 |
| 7485574 |
Methods of forming a metal line in a semiconductor device |
Feb. 3, 2009 |
| 7482694 |
Semiconductor device and its manufacturing method |
Jan. 27, 2009 |
| 7473986 |
Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof |
Jan. 6, 2009 |
| 7470981 |
Semiconductor device with varying dummy via-hole plug density |
Dec. 30, 2008 |
| 7470615 |
Semiconductor structure with self-aligned device contacts |
Dec. 30, 2008 |
| 7470553 |
Built-in design edit structures |
Dec. 30, 2008 |
| 7465662 |
Method of making semiconductor device |
Dec. 16, 2008 |
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