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Class Information
Number: 257/E21.576
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo)
Description: This subclass is indented under subclass E21.575. This subclass is substantially the same in scope as ECLA classification H01L21/768B.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.584 Barrier, adhesion or liner layer (epo) 2,616
257/E21.589 By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (epo) 612
257/E21.577 By forming via holes (epo) 2,177
257/E21.582 Characterized by formation and post treatment of conductors, e.g., patterning (epo) 1,556
257/E21.581 Dielectric comprising air gaps (epo) 539
257/E21.585 Filling of holes, grooves, vias or trenches with conductive material (epo) 2,071
257/E21.59 Local interconnects; local pads (epo) 1,062
257/E21.591 Modifying pattern or conductivity of conductive members, e.g., formation of alloys, reduction of contact resistances (epo) 337
257/E21.583 Planarization; smoothing (epo) 781
257/E21.58 Planarizing dielectric (epo) 592


Patents under this class:

Patent Number Title Of Patent Date Issued
8629508 Semiconductor device and method of manufacture Jan. 14, 2014
8592304 Method for filling metal Nov. 26, 2013
8580697 CVD flowable gap fill Nov. 12, 2013
8580675 Two-track cross-connect in double-patterned structure using rectangular via Nov. 12, 2013
8575020 Pattern-split decomposition strategy for double-patterned lithography process Nov. 5, 2013
8558350 Metal-oxide-metal capacitor structure Oct. 15, 2013
8551881 Method of bevel trimming three dimensional semiconductor device Oct. 8, 2013
8487375 Semiconductor device and method of manufacturing semiconductor device Jul. 16, 2013
8486824 Enhancing metal/low-K interconnect reliability using a protection layer Jul. 16, 2013
8470187 Method of depositing film with tailored comformality Jun. 25, 2013
8461038 Two-track cross-connects in double-patterned metal layers using a forbidden zone Jun. 11, 2013
8460946 Methods of processing and inspecting semiconductor substrates Jun. 11, 2013
8455267 Magnetic tunnel junction device and fabrication Jun. 4, 2013
8450854 Interconnect structures with patternable low-k dielectrics and method of fabricating same May. 28, 2013
8445377 Mechanically robust metal/low-k interconnects May. 21, 2013
8440579 Re-establishing surface characteristics of sensitive low-k dielectrics in microstructure device by using an in situ surface modification May. 14, 2013
8435883 Post passivation interconnection schemes on top of IC chips May. 7, 2013
8405192 Low dielectric constant material Mar. 26, 2013
8372743 Hybrid pitch-split pattern-split lithography process Feb. 12, 2013
8358007 Integrated circuit system employing low-k dielectrics and method of manufacture thereof Jan. 22, 2013
8357608 Multi component dielectric layer Jan. 22, 2013
8338297 Selective metal deposition over dielectric layers Dec. 25, 2012
8324022 Electronic system and method for manufacturing a three-dimensional electronic system Dec. 4, 2012
8318599 Resin layer formation method and semiconductor device fabrication method Nov. 27, 2012
8314005 Homogeneous porous low dielectric constant materials Nov. 20, 2012
8273652 Semiconductor memory device and method of manufacturing the same Sep. 25, 2012
8252680 Methods and architectures for bottomless interconnect vias Aug. 28, 2012
8252659 Method for producing interconnect structures for integrated circuits Aug. 28, 2012
8236639 Semiconductor device manufacturing method Aug. 7, 2012
8183166 Dielectric layer structure and manufacturing method thereof May. 22, 2012
8183154 Selective metal deposition over dielectric layers May. 22, 2012
8173490 Fabrication of electronic devices including flexible electrical circuits May. 8, 2012
8168742 Crosslinkable fluorinated aromatic prepolymer and its uses May. 1, 2012
8158536 Low dielectric constant films and manufacturing method thereof, as well as electronic parts using the same Apr. 17, 2012
8158509 Method of manufacturing semiconductor device Apr. 17, 2012
8143162 Interconnect structure having a silicide/germanide cap layer Mar. 27, 2012
8129776 Semiconductor device Mar. 6, 2012
8129268 Self-aligned lower bottom electrode Mar. 6, 2012
8115311 Wiring structure in a semiconductor device Feb. 14, 2012
8101531 Plasma-activated deposition of conformal films Jan. 24, 2012
8101513 Manufacture method for semiconductor device using damascene method Jan. 24, 2012
8093705 Dual face package having resin insulating layer Jan. 10, 2012
8084862 Interconnect structures with patternable low-k dielectrics and method of fabricating same Dec. 27, 2011
8084826 Semiconductor device and manufacturing method thereof Dec. 27, 2011
8084294 Method of fabricating organic silicon film, semiconductor device including the same, and method of fabricating the semiconductor device Dec. 27, 2011
8072071 Semiconductor device including conductive element Dec. 6, 2011
8072070 Low fabrication cost, fine pitch and high reliability solder bump Dec. 6, 2011
8053272 Semiconductor device fabrication method Nov. 8, 2011
8043959 Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity Oct. 25, 2011
8034725 Method of eliminating small bin defects in high throughput TEOS films Oct. 11, 2011











 
 
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