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Class Information
Number: 257/E21.575
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo)
Description: This subclass is indented under subclass E21.536. This subclass is substantially the same in scope as ECLA classification H01L21/768.


Sub-classes under this class:

Class Number Class Name Patents
257/E21.576 Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) 1,965
257/E21.597 Formed through semiconductor substrate (epo) 387


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12

Patent Number Title Of Patent Date Issued
7615481 Method of manufacturing multilevel interconnect structure and multilevel interconnect structure Nov. 10, 2009
7615486 Apparatus and method for integrated surface treatment and deposition for copper interconnect Nov. 10, 2009
7615488 Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device Nov. 10, 2009
7615489 Method for forming metal interconnects and reducing metal seed layer overhang Nov. 10, 2009
7615474 Method for manufacturing semiconductor device with reduced damage to metal wiring layer Nov. 10, 2009
7611982 Method of forming sheet having foreign material portions used for forming multi-layer wiring board and sheet having foreign portions Nov. 3, 2009
7612453 Semiconductor device having an interconnect structure and a reinforcing insulating film Nov. 3, 2009
7608476 Electronic device Oct. 27, 2009
7592249 Method for manufacturing a semiconductor device Sep. 22, 2009
7592259 Methods and systems for barrier layer surface passivation Sep. 22, 2009
7588950 Test pattern for reliability measurement of copper interconnection line having moisture window and method for manufacturing the same Sep. 15, 2009
7589011 Semiconductor device and method of forming intermetal dielectric layer Sep. 15, 2009
7586192 Routing configuration for high frequency signals in an integrated circuit package Sep. 8, 2009
7585768 Combined copper plating method to improve gap fill Sep. 8, 2009
7579272 Methods of forming low-k dielectric layers containing carbon nanostructures Aug. 25, 2009
7576006 Protective self-aligned buffer layers for damascene interconnects Aug. 18, 2009
7569468 Method for forming a floating gate memory with polysilicon local interconnects Aug. 4, 2009
7560800 Die seal with reduced noise coupling Jul. 14, 2009
7557447 Semiconductor device and method for manufacturing same Jul. 7, 2009
7557029 Semiconductor device and fabrication process thereof Jul. 7, 2009
7553760 Sub-lithographic nano interconnect structures, and method for forming same Jun. 30, 2009
7541278 Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment Jun. 2, 2009
7538023 Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area May. 26, 2009
7531445 Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane May. 12, 2009
7531439 Method for forming an integrated semiconductor circuit arrangement May. 12, 2009
7524758 Interconnect structure and method for semiconductor device Apr. 28, 2009
7524759 Post passivation interconnection schemes on top of IC chip Apr. 28, 2009
7525174 High performance system-on-chip using post passivation process Apr. 28, 2009
7521357 Methods of forming metal wiring in semiconductor devices using etch stop layers Apr. 21, 2009
7521351 Method for forming a semiconductor product and semiconductor product Apr. 21, 2009
7521349 Fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus Apr. 21, 2009
7517736 Structure and method of chemically formed anchored metallic vias Apr. 14, 2009
7517793 Method of forming metal wire in semiconductor device Apr. 14, 2009
7514353 Contact metallization scheme using a barrier layer over a silicide layer Apr. 7, 2009
7514793 Metal interconnection lines of semiconductor devices and methods of forming the same Apr. 7, 2009
7501342 Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same Mar. 10, 2009
7498250 Shapes-based migration of aluminum designs to copper damascene Mar. 3, 2009
7498254 Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement Mar. 3, 2009
7498253 Local interconnection method and structure for use in semiconductor device Mar. 3, 2009
7494926 Method for forming highly conductive metal pattern on flexible substrate and EMI filter using metal pattern formed by the method Feb. 24, 2009
7495340 Metal layer structure of semiconductor device Feb. 24, 2009
7491638 Method of forming an insulating capping layer for a copper metallization layer Feb. 17, 2009
7491636 Methods for forming flexible column die interconnects and resulting structures Feb. 17, 2009
7488624 Techniques for providing decoupling capacitance Feb. 10, 2009
7482272 Through chip connection Jan. 27, 2009
7479670 Organic electronic component with high resolution structuring, and method of the production thereof Jan. 20, 2009
7476604 Aggressive cleaning process for semiconductor device contact formation Jan. 13, 2009
7470968 T-coil apparatus and method for compensating capacitance Dec. 30, 2008
7459790 Post passivation interconnection schemes on top of the IC chips Dec. 2, 2008
7446037 Cladded silver and silver alloy metallization for improved adhesion and electromigration resistance Nov. 4, 2008

1 2 3 4 5 6 7 8 9 10 11 12


 
 
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