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Class Information
Number: 257/E21.571
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using selective deposition of single crystal silicon, i.e., seg technique (epo)
Description: This subclass is indented under subclass E21.545. This subclass is substantially the same in scope as ECLA classification H01L21/762E.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7605074 |
Chemical mechanical polishing and method for manufacturing semiconductor device using the same |
Oct. 20, 2009 |
| 7588980 |
Methods of controlling morphology during epitaxial layer formation |
Sep. 15, 2009 |
| 7579254 |
Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations |
Aug. 25, 2009 |
| 7579617 |
Semiconductor device and production method thereof |
Aug. 25, 2009 |
| 7573123 |
Semiconductor device and method for forming the same |
Aug. 11, 2009 |
| 7531395 |
Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors |
May. 12, 2009 |
| 7528493 |
Interconnect structure and method of fabrication of same |
May. 5, 2009 |
| 7525137 |
TFT mask ROM and method for making same |
Apr. 28, 2009 |
| 7364990 |
Epitaxial crystal growth process in the manufacturing of a semiconductor device |
Apr. 29, 2008 |
| 7202124 |
Strained gettering layers for semiconductor processes |
Apr. 10, 2007 |
| 6559035 |
Method for manufacturing an SOI wafer |
May. 6, 2003 |
| 6404034 |
CMOS circuit with all-around dielectrically insulated source-drain regions |
Jun. 11, 2002 |
| 6350659 |
Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate |
Feb. 26, 2002 |
| 6124156 |
Process for manufacturing a CMOS circuit with all-around dielectrically insulated source-drain regions |
Sep. 26, 2000 |
| 5976959 |
Method for forming large area or selective area SOI |
Nov. 2, 1999 |
| 5948162 |
Method for forming SOI structure |
Sep. 7, 1999 |
| 5950097 |
Advanced isolation scheme for deep submicron technology |
Sep. 7, 1999 |
| 5926721 |
Isolation method for semiconductor device using selective epitaxial growth |
Jul. 20, 1999 |
| 5897939 |
Substrate of the silicon on insulator type for the production of transistors and preparation process for such a substrate |
Apr. 27, 1999 |
| 5854509 |
Method of fabricating semiconductor device and semiconductor device |
Dec. 29, 1998 |
| 5780343 |
Method of producing high quality silicon surface for selective epitaxial growth of silicon |
Jul. 14, 1998 |
| 5773351 |
Isolation layer of semiconductor device and method for fabricating the same |
Jun. 30, 1998 |
| 5668043 |
Method for forming isolated regions in a semiconductor device |
Sep. 16, 1997 |
| 5600161 |
Sub-micron diffusion area isolation with Si-SEG for a DRAM array |
Feb. 4, 1997 |
| 5559353 |
Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof |
Sep. 24, 1996 |
| 5554562 |
Advanced isolation scheme for deep submicron technology |
Sep. 10, 1996 |
| 5548154 |
Isoplanar isolated active regions |
Aug. 20, 1996 |
| 5541136 |
Method of forming a field oxide film in a semiconductor device |
Jul. 30, 1996 |
| 5453396 |
Sub-micron diffusion area isolation with SI-SEG for a DRAM array |
Sep. 26, 1995 |
| 5417180 |
Method for forming SOI structure |
May. 23, 1995 |
| 5384473 |
Semiconductor body having element formation surfaces with different orientations |
Jan. 24, 1995 |
| 5378644 |
Method for manufacturing a semiconductor device |
Jan. 3, 1995 |
| 5304834 |
Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets |
Apr. 19, 1994 |
| 5266517 |
Method for forming a sealed interface on a semiconductor device |
Nov. 30, 1993 |
| 5250837 |
Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
Oct. 5, 1993 |
| 5250461 |
Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
Oct. 5, 1993 |
| 5236863 |
Isolation process for VLSI |
Aug. 17, 1993 |
| 5236546 |
Process for producing crystal article |
Aug. 17, 1993 |
| 5212112 |
Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets |
May. 18, 1993 |
| 5208167 |
Method for producing SOI substrate |
May. 4, 1993 |
| 5185286 |
Process for producing laminated semiconductor substrate |
Feb. 9, 1993 |
| 5135884 |
Method of producing isoplanar isolated active regions |
Aug. 4, 1992 |
| 5134090 |
Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy |
Jul. 28, 1992 |
| 5100830 |
Method of manufacturing a semiconductor device |
Mar. 31, 1992 |
| 5084407 |
Method for planarizing isolated regions |
Jan. 28, 1992 |
| 5084419 |
Method of manufacturing semiconductor device using chemical-mechanical polishing |
Jan. 28, 1992 |
| 5079183 |
C-MOS device and a process for manufacturing the same |
Jan. 7, 1992 |
| 5073516 |
Selective epitaxial growth process flow for semiconductor technologies |
Dec. 17, 1991 |
| 5057443 |
Method for fabricating a trench bipolar transistor |
Oct. 15, 1991 |
| 5034342 |
Method of forming semiconductor stalk structure by epitaxial growth in trench |
Jul. 23, 1991 |
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