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Class Information
Number: 257/E21.565
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using semiconductor or insulator technology, i.e., soi technology (epo) > Using full isolation by porous oxide silicon, i.e., fipos technique (epo)
Description: This subclass is indented under subclass E21.561. This subclass is substantially the same in scope as ECLA classification H01L21/762D4.










Patents under this class:

Patent Number Title Of Patent Date Issued
8652929 CMOS device for reducing charge sharing effect and fabrication method thereof Feb. 18, 2014
8216933 Krypton sputtering of low resistivity tungsten Jul. 10, 2012
7768089 Semiconductor device Aug. 3, 2010
7723760 Semiconductor-based porous structure enabled by capillary force May. 25, 2010
7659581 Transistor with dielectric stressor element fully underlying the active semiconductor region Feb. 9, 2010
7297608 Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition Nov. 20, 2007
7256145 Manufacture of semiconductor device having insulation film of high dielectric constant Aug. 14, 2007
7172930 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer Feb. 6, 2007
6869858 Shallow trench isolation planarized by wet etchback and chemical mechanical polishing Mar. 22, 2005
6808967 Method for producing a buried layer of material in another material Oct. 26, 2004
6376859 Variable porosity porous silicon isolation Apr. 23, 2002
6331456 Fipos method of forming SOI CMOS structure Dec. 18, 2001
5950094 Method for fabricating fully dielectric isolated silicon (FDIS) Sep. 7, 1999
5856229 Process for production of semiconductor substrate Jan. 5, 1999
5840616 Method for preparing semiconductor member Nov. 24, 1998
5548154 Isoplanar isolated active regions Aug. 20, 1996
5433168 Method of producing semiconductor substrate Jul. 18, 1995
5387541 Method of making silicon-on-porous-silicon by ion implantation Feb. 7, 1995
5156896 Silicon substrate having porous oxidized silicon layers and its production method Oct. 20, 1992
5135884 Method of producing isoplanar isolated active regions Aug. 4, 1992
5091061 Silicon substrate having porous oxidized silicon layers and its production method Feb. 25, 1992
5023200 Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies Jun. 11, 1991
4819037 Semiconductor device Apr. 4, 1989
4814287 Method of manufacturing a semiconductor integrated circuit device Mar. 21, 1989
4459181 Semiconductor pattern definition by selective anodization Jul. 10, 1984
4369561 Process for aligning diffusion masks with respect to isolating walls of coffers in integrated circuits Jan. 25, 1983
4282538 Method of integrating semiconductor components Aug. 4, 1981
4199860 Method of integrating semiconductor components Apr. 29, 1980
4180416 Thermal migration-porous silicon technique for forming deep dielectric isolation Dec. 25, 1979
4130542 Polyurethanes stabilized against ultraviolet light and nitrogen oxide deterioration Dec. 19, 1978
4056415 Method for providing electrical isolating material in selected regions of a semiconductive material Nov. 1, 1977
4016017 Integrated circuit isolation structure and method for producing the isolation structure Apr. 5, 1977
3954523 Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation May. 4, 1976











 
 
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