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Class Information
Number: 257/E21.555
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using local oxidation of silicon, e.g., locos, swami, silo (epo) > In region recessed from surface, e.g., in recess, groove, tub or trench region (epo) > Recessed region having shape other than rectangular, e.g., rounded or oblique shape (epo)
Description: This subclass is indented under subclass E21.553. This subclass is substantially the same in scope as ECLA classification H01L21/762B2C.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7446012 |
Lateral PNP transistor and the method of manufacturing the same |
Nov. 4, 2008 |
| 7439140 |
Formation of standard voltage threshold and low voltage threshold MOSFET devices |
Oct. 21, 2008 |
| 7365413 |
Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern |
Apr. 29, 2008 |
| 7314792 |
Method for fabricating transistor of semiconductor device |
Jan. 1, 2008 |
| 7247555 |
Method to control dual damascene trench etch profile and trench depth uniformity |
Jul. 24, 2007 |
| 6849947 |
Semiconductor device and pattern layout method thereof |
Feb. 1, 2005 |
| 6831348 |
Integrated circuit isolation system |
Dec. 14, 2004 |
| 6820246 |
Pattern layout method of semiconductor device |
Nov. 16, 2004 |
| 6812148 |
Preventing gate oxice thinning effect in a recess LOCOS process |
Nov. 2, 2004 |
| 6742169 |
Semiconductor device |
May. 25, 2004 |
| 6613651 |
Integrated circuit isolation system |
Sep. 2, 2003 |
| 6579777 |
Method of forming local oxidation with sloped silicon recess |
Jun. 17, 2003 |
| 6475875 |
Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer |
Nov. 5, 2002 |
| 6461070 |
Document folder and method |
Oct. 8, 2002 |
| 6448157 |
Fabrication process for a semiconductor device |
Sep. 10, 2002 |
| 6444539 |
Method for producing a shallow trench isolation filled with thermal oxide |
Sep. 3, 2002 |
| 6429091 |
Patterned buried insulator |
Aug. 6, 2002 |
| 6399462 |
Method and structure for isolating integrated circuit components and/or semiconductor active devices |
Jun. 4, 2002 |
| 6316300 |
Method of manufacturing a semiconductor device having an oxidation process for selectively forming an oxide film |
Nov. 13, 2001 |
| 6291311 |
Semiconductor device and method for producing same |
Sep. 18, 2001 |
| 6261966 |
Method for improving trench isolation |
Jul. 17, 2001 |
| 6255191 |
Method of fabricating an isolation structure in an integrated circuit |
Jul. 3, 2001 |
| 6249035 |
LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect |
Jun. 19, 2001 |
| 6232646 |
Shallow trench isolation filled with thermal oxide |
May. 15, 2001 |
| 6214700 |
Semiconductor device and method for producing same |
Apr. 10, 2001 |
| 6133115 |
Formation of gate electrode |
Oct. 17, 2000 |
| 6071793 |
Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect |
Jun. 6, 2000 |
| 6046483 |
Planar isolation structure in an integrated circuit |
Apr. 4, 2000 |
| 6033991 |
Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation |
Mar. 7, 2000 |
| 6033971 |
Semiconductor device having an element isolating oxide film and method of manufacturing the same |
Mar. 7, 2000 |
| 6027985 |
Method for forming element isolating film of semiconductor device |
Feb. 22, 2000 |
| 6008106 |
Micro-trench oxidation by using rough oxide mask for field isolation |
Dec. 28, 1999 |
| 5998280 |
Modified recessed locos isolation process for deep sub-micron device processes |
Dec. 7, 1999 |
| 5956599 |
Method for forming isolation layer in semiconductor device |
Sep. 21, 1999 |
| 5940719 |
Method for forming element isolating film of semiconductor device |
Aug. 17, 1999 |
| 5866467 |
Method of improving oxide isolation in a semiconductor device |
Feb. 2, 1999 |
| 5834360 |
Method of forming an improved planar isolation structure in an integrated circuit |
Nov. 10, 1998 |
| 5831323 |
Semiconductor device having an element isolating oxide film and method of manufacturing the same |
Nov. 3, 1998 |
| 5471091 |
Techniques for via formation and filling |
Nov. 28, 1995 |
| 5466624 |
Isolation between diffusion lines in a memory array |
Nov. 14, 1995 |
| 5466624 |
Isolation between diffusion lines in a memory array |
Nov. 14, 1995 |
| 5441094 |
Trench planarization techniques |
Aug. 15, 1995 |
| 5413966 |
Shallow trench etch |
May. 9, 1995 |
| 5393693 |
"Bird-beak-less" field isolation method |
Feb. 28, 1995 |
| 5371036 |
Locos technology with narrow silicon trench |
Dec. 6, 1994 |
| 5360753 |
Manufacturing method for a semiconductor isolation region |
Nov. 1, 1994 |
| 5312770 |
Techniques for forming isolation structures |
May. 17, 1994 |
| 5298110 |
Trench planarization techniques |
Mar. 29, 1994 |
| 5290396 |
Trench planarization techniques |
Mar. 1, 1994 |
| 5252503 |
Techniques for forming isolation structures |
Oct. 12, 1993 |
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