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Class Information
Number: 257/E21.554
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using local oxidation of silicon, e.g., locos, swami, silo (epo) > In region recessed from surface, e.g., in recess, groove, tub or trench region (epo) > Using auxiliary pillars in recessed region, e.g., to form locos over extended areas (epo)
Description: This subclass is indented under subclass E21.553. This subclass is substantially the same in scope as ECLA classification H01L21/762B2B.










Patents under this class:

Patent Number Title Of Patent Date Issued
8492891 Cu pillar bump with electrolytic metal sidewall protection Jul. 23, 2013
7687368 Semiconductor device manufacturing method Mar. 30, 2010
7436030 Strained MOSFETs on separated silicon layers Oct. 14, 2008
7071073 Process for manufacturing low-cost and high-quality SOI substrates Jul. 4, 2006
7026899 Push/pull actuator for microstructures Apr. 11, 2006
7023069 Method for forming thick dielectric regions using etched trenches Apr. 4, 2006
6979876 Method for forming isolation layer of semiconductor device Dec. 27, 2005
6962831 Method of making a thick microstructural oxide layer Nov. 8, 2005
6869856 Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling Mar. 22, 2005
6852606 Method for forming isolation layer of semiconductor device and semiconductor device Feb. 8, 2005
6815795 High voltage resistive structure integrated on a semiconductor substrate Nov. 9, 2004
6797589 Insulating micro-structure and method of manufacturing same Sep. 28, 2004
6790745 Fabrication of dielectrically isolated regions of silicon in a substrate Sep. 14, 2004
6790751 Semiconductor substrate for a one-chip electronic device and related manufacturing method Sep. 14, 2004
6693019 METHOD OF MANUFACTURING AN ELECTRONIC POWER DEVICE MONOLITHICALLY INTEGRATED ON A SEMICONDUCTOR AND COMPRISING A FIRST POWER REGION, A SECOND REGION, AND AN ISOLATION STRUCTURE OF LIMITED PLAN Feb. 17, 2004
6677658 Advanced isolation process for large memory arrays Jan. 13, 2004
6599812 Manufacturing method for a thick oxide layer Jul. 29, 2003
6566732 High voltage resistive structure integrated on a semiconductor substrate May. 20, 2003
6551937 Process for device using partial SOI Apr. 22, 2003
6518147 Process for manufacturing an SOI wafer by oxidation of buried channels Feb. 11, 2003
6495423 Electronic power device monolithically integrated on a semiconductor and comprising edge protection structures having a limited planar dimension Dec. 17, 2002
6455391 Method of forming structures with buried regions in a semiconductor device Sep. 24, 2002
6451655 Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimens Sep. 17, 2002
6362070 Process for manufacturing a SOI wafer with buried oxide regions without cusps Mar. 26, 2002
6306727 Advanced isolation process for large memory arrays Oct. 23, 2001
6174784 Technique for producing small islands of silicon on insulator Jan. 16, 2001
5756389 Method for forming trench isolation for semiconductor device May. 26, 1998
5747377 Process for forming shallow trench isolation May. 5, 1998
5691230 Technique for producing small islands of silicon on insulator Nov. 25, 1997
5482874 Inversion implant isolation process Jan. 9, 1996
5472903 Isolation technology for sub-micron devices Dec. 5, 1995
5374583 Technology for local oxidation of silicon Dec. 20, 1994
5308786 Trench isolation for both large and small areas by means of silicon nodules after metal etching May. 3, 1994
5289024 Bipolar transistor with diffusion compensation Feb. 22, 1994
RE33096 Semiconductor substrate Oct. 17, 1989
4696095 Process for isolation using self-aligned diffusion process Sep. 29, 1987
4642880 Method for manufacturing a recessed semiconductor device Feb. 17, 1987
4576851 Semiconductor substrate Mar. 18, 1986
4471525 Method for manufacturing semiconductor device utilizing two-step etch and selective oxidation to form isolation regions Sep. 18, 1984
RE31506 Method of manufacturing oxide isolated semiconductor device utilizing selective etching technique Jan. 24, 1984
4295266 Method of manufacturing bulk CMOS integrated circuits Oct. 20, 1981
4211582 Process for making large area isolation trenches utilizing a two-step selective etching technique Jul. 8, 1980
4139442 Reactive ion etching method for producing deep dielectric isolation in silicon Feb. 13, 1979
4111724 Method of manufacturing oxide isolated semiconductor device utilizing selective etching technique Sep. 5, 1978











 
 
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