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Class Information
Number: 257/E21.551
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using trench refilling with dielectric materials (epo) > Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (epo)
Description: This subclass is indented under subclass E21.546. This subclass is substantially the same in scope as ECLA classification H01L21/762C8.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7390717 |
Trench power MOSFET fabrication using inside/outside spacers |
Jun. 24, 2008 |
| 7361546 |
Method of forming conductive stud on vertical memory device |
Apr. 22, 2008 |
| 7358149 |
Substrate isolation in integrated circuits |
Apr. 15, 2008 |
| 7338880 |
Method of fabricating a semiconductor device |
Mar. 4, 2008 |
| 7339252 |
Semiconductor having thick dielectric regions |
Mar. 4, 2008 |
| 7297604 |
Semiconductor device having dual isolation structure and method of fabricating the same |
Nov. 20, 2007 |
| 7279397 |
Shallow trench isolation method |
Oct. 9, 2007 |
| 7276411 |
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same |
Oct. 2, 2007 |
| 7268043 |
Semiconductor device and method of manufacturing the same |
Sep. 11, 2007 |
| 7262110 |
Trench isolation structure and method of formation |
Aug. 28, 2007 |
| 7259069 |
Semiconductor device and method of manufacturing the same |
Aug. 21, 2007 |
| 7259421 |
Non-volatile memory devices having trenches |
Aug. 21, 2007 |
| 7244661 |
Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate |
Jul. 17, 2007 |
| 7238568 |
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same |
Jul. 3, 2007 |
| 7235460 |
Method of forming active and isolation areas with split active patterning |
Jun. 26, 2007 |
| 7232697 |
Semiconductor device having enhanced photo sensitivity and method for manufacture thereof |
Jun. 19, 2007 |
| 7229878 |
Phototransistor of CMOS image sensor and method for fabricating the same |
Jun. 12, 2007 |
| 7199006 |
Planarization method of manufacturing a superjunction device |
Apr. 3, 2007 |
| 7157328 |
Selective etching to increase trench surface area |
Jan. 2, 2007 |
| 7118956 |
Trench capacitor and a method for manufacturing the same |
Oct. 10, 2006 |
| 7071531 |
Trench isolation for semiconductor devices |
Jul. 4, 2006 |
| 7071515 |
Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
Jul. 4, 2006 |
| 7061068 |
Shallow trench isolation structures having uniform and smooth topography |
Jun. 13, 2006 |
| 7060960 |
Solid-state imaging device and method of manufacturing the same |
Jun. 13, 2006 |
| 7052964 |
Strained channel transistor and methods of manufacture |
May. 30, 2006 |
| 7045410 |
Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) |
May. 16, 2006 |
| 7045436 |
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) |
May. 16, 2006 |
| 7038289 |
Deep insulating trench |
May. 2, 2006 |
| 7029997 |
Method of doping sidewall of isolation trench |
Apr. 18, 2006 |
| 6979878 |
Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites |
Dec. 27, 2005 |
| 6979628 |
Methods of forming semiconductor devices having field oxides in trenches and devices formed thereby |
Dec. 27, 2005 |
| 6956266 |
Structure and method for latchup suppression utilizing trench and masked sub-collector implantation |
Oct. 18, 2005 |
| 6946358 |
Method of fabricating shallow trench isolation by ultra-thin SIMOX processing |
Sep. 20, 2005 |
| 6946710 |
Method and structure to reduce CMOS inter-well leakage |
Sep. 20, 2005 |
| 6939773 |
Semiconductor devices and manufacturing methods thereof |
Sep. 6, 2005 |
| 6939779 |
Method of manufacturing semiconductor device |
Sep. 6, 2005 |
| 6933215 |
Process for doping a semiconductor body |
Aug. 23, 2005 |
| 6933203 |
Methods for improving well to well isolation |
Aug. 23, 2005 |
| 6927452 |
Semiconductor device having dual isolation structure and method of fabricating the same |
Aug. 9, 2005 |
| 6924182 |
Strained silicon MOSFET having reduced leakage and method of its formation |
Aug. 2, 2005 |
| 6924217 |
Method of forming trench in semiconductor device |
Aug. 2, 2005 |
| 6908810 |
Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
Jun. 21, 2005 |
| 6890832 |
Radiation hardening method for shallow trench isolation in CMOS |
May. 10, 2005 |
| 6887798 |
STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
May. 3, 2005 |
| 6882025 |
Strained-channel transistor and methods of manufacture |
Apr. 19, 2005 |
| 6856001 |
Trench isolation for semiconductor devices |
Feb. 15, 2005 |
| 6849551 |
Method for forming isolation region in semiconductor device |
Feb. 1, 2005 |
| 6846722 |
Method for isolating a hybrid device in an image sensor |
Jan. 25, 2005 |
| 6844239 |
Method for forming shallow well of semiconductor device using low-energy ion implantation |
Jan. 18, 2005 |
| 6838374 |
Semiconductor integrated circuit device and method of fabricating the same |
Jan. 4, 2005 |
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