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Class Information
Number: 257/E21.546
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Dielectric regions, e.g., epic dielectric isolation, locos; trench refilling techniques, soi technology, use of channel stoppers (epo) > Using trench refilling with dielectric materials (epo)
Description: This subclass is indented under subclass E21.545. This subclass is substantially the same in scope as ECLA classification H01L21/762C.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.548 Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and v-shaped trenches, wide and narrow trenches, shallow and deep trenches (epo) 739
257/E21.547 Dielectric material being obtained by full chemical transformation of nondielectric materials, such as polycrystalline silicon, metals (epo) 116
257/E21.551 Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (epo) 379
257/E21.549 Of trenches having shape other than rectangular or v shape, e.g., rounded corners, oblique or rounded trench walls (epo) 598

Patents under this class:

Patent Number Title Of Patent Date Issued
8703577 Method for fabrication deep trench isolation structure Apr. 22, 2014
8692290 Silicon controlled rectifier structure with improved junction breakdown and leakage control Apr. 8, 2014
8691660 Semiconductor component with trench isolation and corresponding production method Apr. 8, 2014
8691659 Method for forming void-free dielectric layer Apr. 8, 2014
8686535 Trench isolation implantation Apr. 1, 2014
8686534 Trench isolation structure and method for forming the same Apr. 1, 2014
8680597 Method and apparatus for improving gate contact Mar. 25, 2014
8679941 Method to improve wet etch budget in FEOL integration Mar. 25, 2014
8669623 Structure related to a thick bottom dielectric (TBD) for trench-gate devices Mar. 11, 2014
8664080 Vertical ESD protection device Mar. 4, 2014
8658538 Method of fabricating memory device Feb. 25, 2014
8658536 Selective fin cut process Feb. 25, 2014
8652911 Semiconductor device and method of manufacturing the same Feb. 18, 2014
8647988 Memory device and method of fabricating the same Feb. 11, 2014
8637956 Semiconductor devices structures including an isolation structure Jan. 28, 2014
8637916 Semiconductor device with mini SONOS cell Jan. 28, 2014
8633564 Semicondutor isolation structure Jan. 21, 2014
8633113 Method for fabricating a bottom oxide layer in a trench Jan. 21, 2014
8629038 FinFETs with vertical fins and methods for forming the same Jan. 14, 2014
8629037 Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process Jan. 14, 2014
8623726 Method for filling a physical isolation trench and integrating a vertical channel array with a periphery circuit Jan. 7, 2014
8618615 Semiconductor device and fabrication method thereof Dec. 31, 2013
8604535 Non-volatile memory device and method of manufacturing the same Dec. 10, 2013
8603893 Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates Dec. 10, 2013
8603891 Methods for forming vertical memory devices and apparatuses Dec. 10, 2013
8598012 Method for fabricating semiconductor device with buried gates Dec. 3, 2013
8592939 Semiconductor device and manufacturing method thereof Nov. 26, 2013
8580653 Method for fabricating an isolation structure Nov. 12, 2013
8580649 Method for manufacturing semiconductor device Nov. 12, 2013
8569143 Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI) Oct. 29, 2013
8564043 EEPROM cell structure and a method of fabricating the same Oct. 22, 2013
8551858 Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory Oct. 8, 2013
8546855 Charging protection device Oct. 1, 2013
8546216 Nonvolatile semiconductor memory device and method of fabricating the same Oct. 1, 2013
8541865 Semiconductor device with improved ESD protection Sep. 24, 2013
8541278 Method for fabricating super-junction power device with reduced miller capacitance Sep. 24, 2013
8536017 Method of manufacturing semiconductor device Sep. 17, 2013
8530329 Methods of fabricating semiconductor devices having various isolation regions Sep. 10, 2013
8530328 Method for manufacturing semiconductor device Sep. 10, 2013
8524570 Method and apparatus for improving gate contact Sep. 3, 2013
8524569 Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer Sep. 3, 2013
8519481 Voids in STI regions for forming bulk FinFETs Aug. 27, 2013
8507332 Method for manufacturing components Aug. 13, 2013
8501581 Methods of forming semiconductor constructions Aug. 6, 2013
8501578 Semiconductor structure formed without requiring thermal oxidation Aug. 6, 2013
8497184 Method for manufacturing semiconductor device Jul. 30, 2013
8492868 Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer Jul. 23, 2013
8492846 Stress-generating shallow trench isolation structure having dual composition Jul. 23, 2013
8486839 Methods and apparatus to improve reliability of isolated vias Jul. 16, 2013
8486818 Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligne Jul. 16, 2013

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