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Class Information
Number: 257/E21.544
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Pn junction isolation (epo)
Description: This subclass is indented under subclass E21.54. This subclass is substantially the same in scope as ECLA classification H01L21/761.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
5175117 Method for making buried isolation Dec. 29, 1992
5171699 Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication Dec. 15, 1992
5166082 BIMOS transistor devices having bipolar and MOS transistors formed in substrate thereof and process for the fabrication of the same Nov. 24, 1992
5159427 Semiconductor substrate structure for use in power IC device Oct. 27, 1992
5156989 Complementary, isolated DMOS IC technology Oct. 20, 1992
5151378 Self-aligned planar monolithic integrated circuit vertical transistor process Sep. 29, 1992
5151382 Method of manufacturing a semiconductor device by maskless pn junction isolation means Sep. 29, 1992
5141881 Method for manufacturing a semiconductor integrated circuit Aug. 25, 1992
RE34025 Semiconductor device with isolation between MOSFET and control circuit Aug. 11, 1992
5137838 Method of fabricating P-buried layers for PNP devices Aug. 11, 1992
5130778 Semiconductor article and preparation thereof Jul. 14, 1992
5128272 Self-aligned planar monolithic integrated circuit vertical transistor process Jul. 7, 1992
5108944 Method of manufacturing a semiconductor device Apr. 28, 1992
5104817 Method of forming bipolar transistor with integral base emitter load resistor Apr. 14, 1992
5097314 Dielectrically isolated substrate with isolated high and low breakdown voltage elements Mar. 17, 1992
5089862 Monocrystalline three-dimensional integrated circuit Feb. 18, 1992
5082793 Method for making solid state device utilizing ion implantation techniques Jan. 21, 1992
5072287 Semiconductor device and method of manufacturing the same Dec. 10, 1991
5066602 Method of making semiconductor IC including polar transistors Nov. 19, 1991
5065212 Semiconductor device Nov. 12, 1991
5065214 Integrated circuit with complementary junction-isolated bipolar transistors Nov. 12, 1991
5049968 Dielectrically isolated substrate and semiconductor device using the same Sep. 17, 1991
5045911 Lateral PNP transistor and method for forming same Sep. 3, 1991
5045900 Semiconductor device having a vertical power MOSFET fabricated in an isolated form on a semiconductor substrate Sep. 3, 1991
5045492 Method of making integrated circuit with high current transistor and CMOS transistors Sep. 3, 1991
5027183 Isolated semiconductor macro circuit Jun. 25, 1991
5023195 Method for manufacturing a semiconductor integrated circuit including a bipolar transistor Jun. 11, 1991
5001073 Method for making bipolar/CMOS IC with isolated vertical PNP Mar. 19, 1991
4999313 Preparation of a semiconductor article using an amorphous seed to grow single crystal semiconductor material Mar. 12, 1991
4996164 Method for forming lateral PNP transistor Feb. 26, 1991
4969823 Integrated circuit with complementary junction-isolated bipolar transistors and method of making same Nov. 13, 1990
4969030 Integrated structure for a signal transfer network, in particular for a pilot circuit for MOS power transistors Nov. 6, 1990
4965215 Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip Oct. 23, 1990
4947231 Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it Aug. 7, 1990
4946800 Method for making solid-state device utilizing isolation grooves Aug. 7, 1990
4942440 High voltage semiconductor devices with reduced on-resistance Jul. 17, 1990
4940671 High voltage complementary NPN/PNP process Jul. 10, 1990
4939099 Process for fabricating isolated vertical bipolar and JFET transistors Jul. 3, 1990
4936928 Semiconductor device Jun. 26, 1990
4933573 Semiconductor integrated circuit Jun. 12, 1990
4916513 Dielectrically isolated integrated circuit structure Apr. 10, 1990
4914051 Method for making a vertical power DMOS transistor with small signal bipolar transistors Apr. 3, 1990
4910160 High voltage complementary NPN/PNP process Mar. 20, 1990
4902633 Process for making a bipolar integrated circuit Feb. 20, 1990
4898839 Semiconductor integrated circuit and manufacturing method therefor Feb. 6, 1990
4898836 Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another Feb. 6, 1990
4897704 Lateral bipolar transistor with polycrystalline lead regions Jan. 30, 1990
4897363 Method of manufacturing semiconductor device isolation Jan. 30, 1990
4889822 Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities Dec. 26, 1989
4889492 High capacitance trench capacitor and well extension process Dec. 26, 1989

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