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Class Information
Number: 257/E21.544
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of isolation regions between components (epo) > Pn junction isolation (epo)
Description: This subclass is indented under subclass E21.54. This subclass is substantially the same in scope as ECLA classification H01L21/761.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
5895251 Method for forming a triple-well in a semiconductor device Apr. 20, 1999
5892268 Inductive load driving and control circuits inside isolation regions Apr. 6, 1999
5882977 Method of forming a self-aligned, sub-minimum isolation ring Mar. 16, 1999
5849614 Method of isolation by active transistors with grounded gates Dec. 15, 1998
5841169 Integrated circuit containing devices dielectrically isolated and junction isolated from a substrate Nov. 24, 1998
5837553 Method of making high voltage, junction isolation semiconductor device having dual conductivity type buried regions Nov. 17, 1998
5830772 Method for fabricating isolating regions for buried conductors Nov. 3, 1998
5830783 Monolithic semiconductor device having an edge structure and method for producing said structure Nov. 3, 1998
5821600 Isolation by active transistors with grounded gates Oct. 13, 1998
5821145 Method for isolating elements in a semiconductor device Oct. 13, 1998
5814866 Semiconductor device having at least one field oxide area and CMOS vertically modulated wells (VMW) with a buried implanted layer for lateral isolation having a first portion below a well, a s Sep. 29, 1998
5759902 Method of making an integrated circuit with complementary junction-isolated bipolar transistors Jun. 2, 1998
5753964 Semiconductor device for a motor driving circuit May. 19, 1998
5750442 Germanium as an antireflective coating and method of use May. 12, 1998
5726476 Semiconductor device having a particular CMOS structure Mar. 10, 1998
5702959 Method for making an isolated vertical transistor Dec. 30, 1997
5679586 Composite mask process for semiconductor fabrication Oct. 21, 1997
5670821 Guard ring for mitigation of parasitic transistors in junction isolated integrated circuits Sep. 23, 1997
5665630 Device separation structure and semiconductor device improved in wiring structure Sep. 9, 1997
5623159 Integrated circuit isolation structure for suppressing high-frequency cross-talk Apr. 22, 1997
5597742 Semiconductor device and method Jan. 28, 1997
5567978 High voltage, junction isolation semiconductor device having dual conductivity tape buried regions and its process of manufacture Oct. 22, 1996
5529939 Method of making an integrated circuit with complementary isolated bipolar transistors Jun. 25, 1996
5512774 Dielectrically isolated substrate and semiconductor device using the same Apr. 30, 1996
5501993 Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation Mar. 26, 1996
5497026 Semiconductor device with improved breakdown voltage characteristics Mar. 5, 1996
5485027 Isolated DMOS IC technology Jan. 16, 1996
5455437 Semiconductor device having crystalline defect isolation regions Oct. 3, 1995
5449936 High current MOS transistor bridge structure Sep. 12, 1995
5444291 Integrated bridge device for optimizing conduction power losses Aug. 22, 1995
5432376 Semiconductor devices containing power and control transistors Jul. 11, 1995
5394007 Isolated well and method of making Feb. 28, 1995
5376565 Fabrication of lateral bipolar transistor Dec. 27, 1994
5374582 Laminated substrate for semiconductor device and manufacturing method thereof Dec. 20, 1994
5364802 Method of making a semiconductor device with buried electrode Nov. 15, 1994
5340766 Method for fabricating charge-coupled device Aug. 23, 1994
5332920 Dielectrically isolated high and low voltage substrate regions Jul. 26, 1994
5316964 Method of forming integrated circuits with diffused resistors in isolation regions May. 31, 1994
5317180 Vertical DMOS transistor built in an n-well MOS-based BiCMOS process May. 31, 1994
5306934 Semiconductor device with buried electrode Apr. 26, 1994
5302848 Integrated circuit with complementary junction-isolated bipolar transistors Apr. 12, 1994
5273912 Method for manufacturing semiconductor device Dec. 28, 1993
5268312 Method of forming isolated wells in the fabrication of BiCMOS devices Dec. 7, 1993
5262345 Complimentary bipolar/CMOS fabrication method Nov. 16, 1993
5208171 Process for preparing BiCMOS semiconductor device May. 4, 1993
5200639 Semiconductor device with isolating groove containing single crystalline aluminum wiring Apr. 6, 1993
5192712 Control and moderation of aluminum in silicon using germanium and germanium with boron Mar. 9, 1993
5182219 Push-back junction isolation semiconductor structure and method Jan. 26, 1993
5179432 Integrated PNP power bipolar transistor with low injection into substrate Jan. 12, 1993
5177587 Push-back junction isolation semiconductor structure and method Jan. 5, 1993

1 2 3 4 5 6 7 8 9 10 11

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