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Class Information
Number: 257/E21.537
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Making of localized buried regions, e.g., buried collector layer, internal connection, substrate contacts (epo)
Description: This subclass is indented under subclass E21.536. This subclass is substantially the same in scope as ECLA classification H01L21/74.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.539 For group iii-v compound semiconductor integrated circuits (epo) 12
257/E21.538 Making of internal connections, substrate contacts (epo) 440


Patents under this class:
1 2 3 4 5 6 7

Patent Number Title Of Patent Date Issued
8629026 Source tip optimization for high voltage transistor devices Jan. 14, 2014
8557691 Method of fabricating semiconductor device having buried wiring and related device Oct. 15, 2013
8420495 Manufacturing approach for collector and a buried layer of bipolar transistor Apr. 16, 2013
8288185 Semiconductor devices and methods of forming the same Oct. 16, 2012
8222114 Manufacturing approach for collector and a buried layer of bipolar transistor Jul. 17, 2012
8183146 Manufacturing method for a buried circuit structure May. 22, 2012
8138570 Isolated junction field-effect transistor Mar. 20, 2012
8119471 Semiconductor device and method for manufacturing the same Feb. 21, 2012
8119512 Method for fabricating semiconductor device with damascene bit line Feb. 21, 2012
8101515 Methods of manufacturing semiconductor devices having contact plugs in insulation layers Jan. 24, 2012
8049270 Semiconductor device Nov. 1, 2011
8022496 Semiconductor structure and method of manufacture Sep. 20, 2011
8003475 Method for fabricating a transistor structure Aug. 23, 2011
7977768 Semiconductor devices and methods of manufacture thereof Jul. 12, 2011
7910482 Method of forming a finFET and structure Mar. 22, 2011
7829368 Methods of forming double pinned photodiodes Nov. 9, 2010
7816763 BJT and method for fabricating the same Oct. 19, 2010
7790617 Formation of metal silicide layer over copper interconnect for reliability enhancement Sep. 7, 2010
7785974 Methods of employing a thin oxide mask for high dose implants Aug. 31, 2010
7763936 Lateral MOS device with minimization of parasitic elements Jul. 27, 2010
7732323 Methods of manufacturing semiconductor devices having contact plugs in insulation layers Jun. 8, 2010
7705348 Semiconductor light-emitting device with electrode for N-polar InGaAIN surface Apr. 27, 2010
7691734 Deep trench based far subcollector reachthrough Apr. 6, 2010
7666750 Bipolar device having improved capacitance Feb. 23, 2010
7651883 High energy implant photodiode stack Jan. 26, 2010
7651906 Integrated circuit devices having a stress buffer spacer and methods of fabricating the same Jan. 26, 2010
7589009 Method for fabricating a top conductive layer in a semiconductor die and related structure Sep. 15, 2009
7465632 Method for forming buried doped region Dec. 16, 2008
7442602 Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other Oct. 28, 2008
7315083 Circuit device and manufacturing method thereof Jan. 1, 2008
7294561 Internal gettering in SIMOX SOI silicon substrates Nov. 13, 2007
7262122 Method of forming metal line in semiconductor memory device Aug. 28, 2007
7256119 Semiconductor device having trench structures and method Aug. 14, 2007
7223694 Method for improving selectivity of electroless metal deposition May. 29, 2007
7205219 Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate Apr. 17, 2007
7180152 Process for resurf diffusion for high voltage MOSFET Feb. 20, 2007
7161198 Semiconductor integrated circuit device having MOS transistor Jan. 9, 2007
7144829 Method for fabricating semiconductor device and semiconductor substrate Dec. 5, 2006
7052966 Deep N wells in triple well structures and method for fabricating same May. 30, 2006
7049169 Method of fabricating a semiconductor device May. 23, 2006
6946364 Integrated circuit having a device wafer with a diffused doped backside layer Sep. 20, 2005
6894348 Semiconductor device May. 17, 2005
6884701 Process for fabricating semiconductor device Apr. 26, 2005
6869851 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps Mar. 22, 2005
6867495 Integrated circuit having a device wafer with a diffused doped backside layer Mar. 15, 2005
6815301 Method for fabricating bipolar transistor Nov. 9, 2004
6720238 Method for manufacturing buried areas Apr. 13, 2004
6716709 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps Apr. 6, 2004
6624497 Semiconductor device with a reduced mask count buried layer Sep. 23, 2003
6600200 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors Jul. 29, 2003

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