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Class Information
Number: 257/E21.522
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Testing or measuring during manufacture or treatment or reliability measurement, i.e., testing of parts followed by no processing which modifies parts as such (epo) > Structural arrangement (epo)
Description: This subclass is indented under subclass E21.521. This subclass is substantially the same in scope as ECLA classification H01L21/66A.
Sub-classes under this class:
| Class Number |
Class Name |
Patents |
| 257/E21.523 |
Additional lead-in metallization on device, e.g., additional pads or lands, lines in scribe line, sacrificed conductors, sacrificed frames (epo) |
24 |
| 257/E21.524 |
Circuit for characterizing or monitoring manufacturing process, e.g., whole test die, wafer filled with test structures, onboard devices incorporated on each die, process/product control monitors or pcm, devices in scribe-line/kerf, drop-in devices (epo) |
34 |
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7608470 |
Interconnection device including one or more embedded vias and method of producing the same |
Oct. 27, 2009 |
| 7602064 |
Semiconductor device having an inspection hole striding a boundary |
Oct. 13, 2009 |
| 7598100 |
Manufacturing method of semiconductor integrated circuit device |
Oct. 6, 2009 |
| 7592623 |
Semiconductor device including wiring connection testing structure |
Sep. 22, 2009 |
| 7588948 |
Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods |
Sep. 15, 2009 |
| 7553678 |
Method for detecting semiconductor manufacturing conditions |
Jun. 30, 2009 |
| 7550382 |
Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device |
Jun. 23, 2009 |
| 7498604 |
Deposition stop time detection apparatus and methods for fabricating copper using the same |
Mar. 3, 2009 |
| 7494930 |
Structure and method for placement, sizing and shaping of dummy structures |
Feb. 24, 2009 |
| 7491556 |
Efficient method of forming and assembling a microelectronic chip including solder bumps |
Feb. 17, 2009 |
| 7465991 |
Semiconductor substrates having useful and transfer layers |
Dec. 16, 2008 |
| 7442559 |
Method for producing an optical or electronic module provided with a plastic package |
Oct. 28, 2008 |
| 7436077 |
Semiconductor device and method of manufacturing the same |
Oct. 14, 2008 |
| 7432593 |
Semiconductor package assembly and method for electrically isolating modules |
Oct. 7, 2008 |
| 7414299 |
Semiconductor package assembly and method for electrically isolating modules |
Aug. 19, 2008 |
| 7381575 |
Device and method for detecting alignment of active areas and memory cell structures in DRAM devices |
Jun. 3, 2008 |
| 7354842 |
Methods of forming conductive materials |
Apr. 8, 2008 |
| 7335969 |
Method of monitoring introduction of interfacial species |
Feb. 26, 2008 |
| 7317204 |
Test structure of semiconductor device |
Jan. 8, 2008 |
| 7303929 |
Reloading of die carriers without removal of die carriers from sockets on test boards |
Dec. 4, 2007 |
| 7271013 |
Semiconductor device having a bond pad and method therefor |
Sep. 18, 2007 |
| 7271408 |
Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors |
Sep. 18, 2007 |
| 7220606 |
Integrated circuit identification |
May. 22, 2007 |
| 7148135 |
Method of designing low-power semiconductor integrated circuit |
Dec. 12, 2006 |
| 7135345 |
Methods for processing semiconductor devices in a singulated form |
Nov. 14, 2006 |
| 7105379 |
Implementation of protection layer for bond pad protection |
Sep. 12, 2006 |
| 6858445 |
Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an integrated circuit |
Feb. 22, 2005 |
| 6281028 |
LED alignment points for semiconductor die |
Aug. 28, 2001 |
| 6274397 |
Method to preserve the testing chip for package's quality |
Aug. 14, 2001 |
| 5981370 |
Method for maximizing interconnection integrity and reliability between integrated circuits and external connections |
Nov. 9, 1999 |
| 5418383 |
Semiconductor device capable of previously evaluating characteristics of power output element |
May. 23, 1995 |
| 5319224 |
Integrated circuit device having a geometry to enhance fabrication and testing and manufacturing method thereof |
Jun. 7, 1994 |
| 5304738 |
System for protecting leads of a semiconductor chip package during testing, burn-in and handling |
Apr. 19, 1994 |
| 5221812 |
System for protecting leads to a semiconductor chip package during testing, burn-in and handling |
Jun. 22, 1993 |
| 4223337 |
Semiconductor integrated circuit with electrode pad suited for a characteristic testing |
Sep. 16, 1980 |
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