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Class Information
Number: 257/E21.508
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Assembling semiconductor devices, e.g., packaging , including mounting, encapsulating, or treatment of packaged semiconductor (epo) > Attaching or detaching leads or other conductive members, to be used for carrying current to or from device in operation (epo) > Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (epo) > Forming solder bumps (epo)
Description: This subclass is indented under subclass E21.507. This subclass is substantially the same in scope as ECLA classification H01L21/60B2.










Patents under this class:

Patent Number Title Of Patent Date Issued
8709932 Integrated circuit packaging system with interconnects and method of manufacture thereof Apr. 29, 2014
8709866 Methods of forming integrated circuit packages Apr. 29, 2014
8691685 Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures Apr. 8, 2014
8680677 Carbon nanotube-based conductive connections for integrated circuit devices Mar. 25, 2014
8679964 Prevention and control of intermetallic alloy inclusions Mar. 25, 2014
8679591 Method for reducing voids in a copper-tin interface and structure formed thereby Mar. 25, 2014
8673684 Semiconductor device and manufacturing method thereof Mar. 18, 2014
8671560 In system reflow of low temperature eutectic bond balls Mar. 18, 2014
8659162 Semiconductor device having an interconnect structure with TSV using encapsulant for structural support Feb. 25, 2014
8659155 Mechanisms for forming copper pillar bumps Feb. 25, 2014
8659123 Metal pad structures in dies Feb. 25, 2014
8659113 Embedded semiconductor die package and method of making the same using metal frame carrier Feb. 25, 2014
8653658 Planarized bumps for underfill control Feb. 18, 2014
8642397 Semiconductor wafer level package (WLP) and method of manufacture thereof Feb. 4, 2014
8637393 Methods and structures for capping a structure with a protective coating Jan. 28, 2014
8633586 Mock bump system for flip chip integrated circuits Jan. 21, 2014
8633582 Chip package and fabrication method thereof Jan. 21, 2014
8624393 Methods and designs for localized wafer thinning Jan. 7, 2014
8624391 Chip design with robust corner bumps Jan. 7, 2014
8617997 Selective wet etching of gold-tin based solder Dec. 31, 2013
8610273 Wafer level chip scale package without an encapsulated via Dec. 17, 2013
8609444 Manufacturing method of mounting part of semiconductor light emitting element, manufacturing method of light emitting device, and semiconductor light emitting element Dec. 17, 2013
8604613 Electronic assembly having a multilayer adhesive structure Dec. 10, 2013
8603859 Integrated circuit packaging system with dual side mold and method of manufacture thereof Dec. 10, 2013
8597978 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint Dec. 3, 2013
8592286 Ultra-thin wafer system and method of manufacture thereof Nov. 26, 2013
8587119 Conductive feature for semiconductor substrate and method of manufacture Nov. 19, 2013
8586467 Method of mounting electronic component and mounting substrate Nov. 19, 2013
8575007 Selective electromigration improvement for high current C4s Nov. 5, 2013
8569162 Conductive bump structure on substrate and fabrication method thereof Oct. 29, 2013
8564128 Semiconductor device and manufacturing method of the same Oct. 22, 2013
8563418 Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces Oct. 22, 2013
8563416 Coaxial solder bump support structure Oct. 22, 2013
8563357 Method of packaging a die Oct. 22, 2013
8558396 Bond pad configurations for semiconductor dies Oct. 15, 2013
8541259 Semiconductor device and manufacturing method thereof Sep. 24, 2013
8536045 Reflow method Sep. 17, 2013
8531041 Semiconductor component having a plated through-hole and method for the production thereof Sep. 10, 2013
8531031 Integrated circuit packages Sep. 10, 2013
8530360 Method for low stress flip-chip assembly of fine-pitch semiconductor devices Sep. 10, 2013
8530346 Process of forming an electronic device including a conductive stud over a bonding pad region Sep. 10, 2013
8525353 Microspring structures adapted for target device cooling Sep. 3, 2013
8524595 Semiconductor package structures Sep. 3, 2013
8524593 Arrangement for solder bump formation on wafers Sep. 3, 2013
8513680 Semiconductor package and method of manufacturing the same Aug. 20, 2013
8513057 Integrated circuit packaging system with routable underlayer and method of manufacture thereof Aug. 20, 2013
8508043 Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump Aug. 13, 2013
8501613 UBM etching methods for eliminating undercut Aug. 6, 2013
8501545 Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime Aug. 6, 2013
8497575 Semiconductor packaging system with an aligned interconnect and method of manufacture thereof Jul. 30, 2013











 
 
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