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Class Information
Number: 257/E21.496
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body other than carbon, si, ge, sic, se, te, cu 2 o, cui, and group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than electromagnetic radiation (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > Deposition of noninsulating, e.g., conductive -, resistive -, layer on insulating layer (epo) > Post treatment of layer (epo)
Description: This subclass is indented under subclass E21.495. This subclass is substantially the same in scope as ECLA classification H01L21/4763B.


Patents under this class:

Patent Number Title Of Patent Date Issued
7375023 Method and apparatus for chemical mechanical polishing of semiconductor substrates May. 20, 2008
7348653 Resistive memory cell, method for forming the same and resistive memory array using the same Mar. 25, 2008
5976962 Method of fabricating semiconductor device Nov. 2, 1999
5955384 Method of fabricating semiconductor device Sep. 21, 1999
5750437 Method of fabricating semiconductor device May. 12, 1998
5681779 Method of doping metal layers for electromigration resistance Oct. 28, 1997



 
 
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