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Class Information
Number: 257/E21.49
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body other than carbon, si, ge, sic, se, te, cu 2 o, cui, and group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than electromagnetic radiation (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic techniques; post treatment of these layers (epo) > Post treatment of insulating layer (epo) > Etching layer (epo)
Description: This subclass is indented under subclass E21.489. This subclass is substantially the same in scope as ECLA classification H01L21/4757B.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7282447 |
Method for an integrated circuit contact |
Oct. 16, 2007 |
| 7262134 |
Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
Aug. 28, 2007 |
| 7244637 |
Chip on board and heat sink attachment methods |
Jul. 17, 2007 |
| 7199059 |
Method for removing polymer as etching residue |
Apr. 3, 2007 |
| 7169637 |
One mask Pt/PCMO/Pt stack etching process for RRAM applications |
Jan. 30, 2007 |
| 7084065 |
Method for fabricating a semiconductor device |
Aug. 1, 2006 |
| 6887796 |
Method of wet etching a silicon and nitrogen containing material |
May. 3, 2005 |
| 5693567 |
Separately etching insulating layer for contacts within array and for peripheral pads |
Dec. 2, 1997 |
| 5157000 |
Method for dry etching openings in integrated circuit layers |
Oct. 20, 1992 |
| 5110410 |
Zinc sulfide planarization |
May. 5, 1992 |
| 5017511 |
Method for dry etching vias in integrated circuit layers |
May. 21, 1991 |
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