Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Physics
Class Information
Number: 257/E21.488
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body other than carbon, si, ge, sic, se, te, cu 2 o, cui, and group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than electromagnetic radiation (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic techniques; post treatment of these layers (epo) > Using mask (epo)
Description: This subclass is indented under subclass E21.487. This subclass is substantially the same in scope as ECLA classification H01L21/475.










Patents under this class:

Patent Number Title Of Patent Date Issued
8673702 Field shield dielectric as a mask during semiconductor ink jet printing Mar. 18, 2014
8309460 Methods of manufacturing semiconductor devices Nov. 13, 2012
8039340 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming Oct. 18, 2011
7986049 Semiconductor device having multiple-layer hard mask with opposite stresses and method for fabricating the same Jul. 26, 2011
7879645 Fill-in etching free pore device Feb. 1, 2011
7781347 Semiconductor device having multiple-layer hard mask with opposite stresses and method for fabricating the same Aug. 24, 2010
7696081 Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns Apr. 13, 2010
7601586 Methods of forming buried bit line DRAM circuitry Oct. 13, 2009
7592265 Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor Sep. 22, 2009
7531450 Method of fabricating semiconductor device having contact hole with high aspect-ratio May. 12, 2009
7148102 Methods of forming buried bit line DRAM circuitry Dec. 12, 2006
5318666 Method for via formation and type conversion in group II and group VI materials Jun. 7, 1994











 
 
  Recently Added Patents
Processes for producing polyunsaturated fatty acids in transgenic organisms
Method and apparatus for information exchange over a web based environment
Method and system for weighted fair queuing
Aromatic amine derivative, organic electroluminescent element employing the same, and process for producing aromatic amine derivative
Communication terminal, communication system, server apparatus, and communication connecting method
Digital broadcasting transmission and reception system, and a signal processing method using turbo processing and turbo decoding
Geo-coding images
  Randomly Featured Patents
Sprinkler base
System and method to provide a ramp having a location which is transitioning from a first grade to a second grade for removing a read/write head from a media
Photomultiplier tube having a plurality of sensing areas
System and method for efficient rectangular to polar signal conversion using cordic algorithm
System and method for simulation of computer systems combining hardware and software interaction
Method and apparatus for selectively generating control signals in a telephone system
Catalyst formulations containing Group 11 metals for hydrogen generation
Wheel
Simultaneous acid fracturing using acids with different densities
Quick release insulator for male or female spade terminals