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Class Information
Number: 257/E21.474
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body other than carbon, si, ge, sic, se, te, cu 2 o, cui, and group iii-v compounds with or without impurities, e.g., doping materials (epo) > Radiation treatment (epo) > With high-energy radiation (epo) > Producing ion implantation (epo) > Using mask (epo)
Description: This subclass is indented under subclass E21.473. This subclass is substantially the same in scope as ECLA classification H01L21/426.










Patents under this class:

Patent Number Title Of Patent Date Issued
8399347 Integrated circuits and methods of forming conductive lines and conductive pads therefor Mar. 19, 2013
7883973 Method of forming semiconductor wells Feb. 8, 2011
7858458 CMOS fabrication Dec. 28, 2010
7799630 Method for manufacturing a CMOS device having dual metal gate Sep. 21, 2010
7682915 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance Mar. 23, 2010
7659187 Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface Feb. 9, 2010
7439163 Methods for fabricating fluid injection devices Oct. 21, 2008











 
 
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