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Class Information
Number: 257/E21.448
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With pn junction or heterojunction gate (epo) > With heterojunction gate (epo)
Description: This subclass is indented under subclass E21.445. This subclass is substantially the same in scope as ECLA classification H01L21/337C.










Patents under this class:

Patent Number Title Of Patent Date Issued
8536620 Integrated circuit including a hetero-interface and self adjusted diffusion method for manufacturing the same Sep. 17, 2013
8338860 Normally off gallium nitride field effect transistors (FET) Dec. 25, 2012
8253168 Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics Aug. 28, 2012
8120072 JFET devices with increased barrier height and methods of making same Feb. 21, 2012
7952088 Semiconducting device having graphene channel May. 31, 2011
7843006 Semiconductor component arrangement having a power transistor and a temperature measuring arrangement Nov. 30, 2010
7795679 Device structures with a self-aligned damage layer and methods for forming such device structures Sep. 14, 2010
7772056 Transistors for replacing metal-oxide semiconductor field-effect transistors in nanoelectronics Aug. 10, 2010
7473587 High-quality SGOI by oxidation near the alloy melting temperature Jan. 6, 2009
7074623 Methods of forming strained-semiconductor-on-insulator finFET device structures Jul. 11, 2006
7074686 Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications Jul. 11, 2006
7071065 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Jul. 4, 2006
7056789 Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor Jun. 6, 2006
6995430 Strained-semiconductor-on-insulator device structures Feb. 7, 2006
6914301 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same Jul. 5, 2005
6905934 Semiconductor device and a method of manufacturing the same Jun. 14, 2005
6900103 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits May. 31, 2005
6869897 Manufacturing method for semiconductor substrate, and semiconductor device having a strained Si layer Mar. 22, 2005
6838728 Buried-channel devices and substrates for fabrication of semiconductor-based devices Jan. 4, 2005
6833569 Self-aligned planar double-gate process by amorphization Dec. 21, 2004
6830976 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Dec. 14, 2004
6828632 Stable PD-SOI devices and methods Dec. 7, 2004
6815310 Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel Nov. 9, 2004
6805962 Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications Oct. 19, 2004
6759695 Integrated circuit metal oxide semiconductor transistor Jul. 6, 2004
6727550 Integrated circuit device Apr. 27, 2004
6724008 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Apr. 20, 2004
6723622 Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer Apr. 20, 2004
6723661 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Apr. 20, 2004
6703688 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Mar. 9, 2004
6703648 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Mar. 9, 2004
6677192 Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Jan. 13, 2004
6649492 Strained Si based layer made by UHV-CVD, and devices therein Nov. 18, 2003
6646322 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Nov. 11, 2003
6633066 CMOS integrated circuit devices and substrates having unstrained silicon active layers Oct. 14, 2003
6620664 Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same Sep. 16, 2003
6620665 Method for fabricating semiconductor device Sep. 16, 2003
6593641 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Jul. 15, 2003
6563152 Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel May. 13, 2003
6525338 Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor Feb. 25, 2003
6461945 Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions Oct. 8, 2002
6455377 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) Sep. 24, 2002
6429457 Field-effect transistor Aug. 6, 2002
6403981 Double gate transistor having a silicon/germanium channel region Jun. 11, 2002
6326667 Semiconductor devices and methods for producing semiconductor devices Dec. 4, 2001
5714777 Si/SiGe vertical junction field effect transistor Feb. 3, 1998
5367184 Vertical JFET transistor with optimized bipolar operating mode and corresponding method of fabrication Nov. 22, 1994











 
 
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