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Class Information
Number: 257/E21.438
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With an insulated gate (epo) > Using self-aligned silicidation, i.e., salicide (epo)
Description: This subclass is indented under subclass E21.409. This subclass is substantially the same in scope as ECLA classification H01L21/336M.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.439 Providing different silicide thicknesses on gate and on source or drain (epo) 115


Patents under this class:

Patent Number Title Of Patent Date Issued
8709897 High performance strained source-drain structure and method of fabricating the same Apr. 29, 2014
8691703 Method of manufacturing semiconductor device Apr. 8, 2014
8679894 Low temperature deposition of phase change memory materials Mar. 25, 2014
8673724 Methods of fabricating semiconductor devices Mar. 18, 2014
8658485 Semiconductor device and method of fabricating the same Feb. 25, 2014
8642439 Semiconductor device and method of formation Feb. 4, 2014
8642435 Performing treatment on stressors Feb. 4, 2014
8642433 Method for manufacturing semiconductor device Feb. 4, 2014
8597975 Method of fabricating a microelectronic device with programmable memory Dec. 3, 2013
8574981 Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same Nov. 5, 2013
8574980 Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device Nov. 5, 2013
8563429 Methods of forming a metal silicide layer for semiconductor devices Oct. 22, 2013
8518765 Aqua regia and hydrogen peroxide HCl combination to remove Ni and NiPt residues Aug. 27, 2013
8507378 Method and structure for self aligned contact for integrated circuits Aug. 13, 2013
8492275 Method to form uniform silicide by selective implantation Jul. 23, 2013
8470703 Semiconductor device and method of fabricating the same Jun. 25, 2013
8405131 High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same Mar. 26, 2013
8343867 Method for main spacer trim-back Jan. 1, 2013
8304342 Sacrificial CMP etch stop layer Nov. 6, 2012
8288198 Low temperature deposition of phase change memory materials Oct. 16, 2012
8273631 Method of fabricating n-channel metal-oxide semiconductor transistor Sep. 25, 2012
8252651 Method of manufacturing semiconductor device Aug. 28, 2012
8236678 Tunable spacers for improved gapfill Aug. 7, 2012
8202799 Methods of manufacturing metal-silicide features Jun. 19, 2012
8193032 Ultrathin spacer formation for carbon-based FET Jun. 5, 2012
8178438 Manufacturing method of semiconductor device and electronic device May. 15, 2012
8168487 Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer May. 1, 2012
8158519 Method of manufacturing non-volatile memory cell using self-aligned metal silicide Apr. 17, 2012
8148262 Method for manufacturing semiconductor device Apr. 3, 2012
8138570 Isolated junction field-effect transistor Mar. 20, 2012
8133746 Method for semiconductor gate hardmask removal and decoupling of implants Mar. 13, 2012
8120120 Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility Feb. 21, 2012
8105946 Method of forming conductive lines of semiconductor memory device Jan. 31, 2012
8105868 Method for making solar sub-cells from a solar cell Jan. 31, 2012
8071437 Method of fabricating efuse, resistor and transistor Dec. 6, 2011
8058132 Method of fabricating flash memory device Nov. 15, 2011
8039388 Main spacer trim-back method for replacement gate process Oct. 18, 2011
8039382 Method for forming self-aligned metal silicide contacts Oct. 18, 2011
8034715 Method of fabricating semiconductor integrated circuit device Oct. 11, 2011
8030716 Self-aligned CMOS structure with dual workfunction Oct. 4, 2011
8021971 Structure and method to form a thermally stable silicide in narrow dimension gate stacks Sep. 20, 2011
8008136 Fully silicided gate structure for FinFET devices Aug. 30, 2011
7989300 Method of manufacturing semiconductor device Aug. 2, 2011
7985652 Metal stress memorization technology Jul. 26, 2011
7977194 Method for fabricating semiconductor device with fully silicided gate electrode Jul. 12, 2011
7960280 Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow Jun. 14, 2011
7939881 Semiconductor device May. 10, 2011
7892970 Alternative methods for fabrication of substrates and heterostructures made of silicon compounds and alloys Feb. 22, 2011
7888264 MOSFET structure with multiple self-aligned silicide contacts Feb. 15, 2011
7867863 Method for forming self-aligned source and drain contacts using a selectively passivated metal gate Jan. 11, 2011











 
 
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