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Class Information
Number: 257/E21.431
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With an insulated gate (epo) > Lateral single gate silicon transistor (epo) > With source and drain recessed by etching or recessed and refi lled (epo)
Description: This subclass is indented under subclass E21.424. This subclass is substantially the same in scope as ECLA classification H01L21/336H8.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8709896 Semiconductor device and fabrication method Apr. 29, 2014
8704310 Trench isolation structure Apr. 22, 2014
8664056 Transistor with embedded strain-inducing material formed in diamond-shaped cavities based on a pre-amorphization Mar. 4, 2014
8659090 Resistive memory and methods for forming the same Feb. 25, 2014
8652947 Non-polar III-V nitride semiconductor and growth method Feb. 18, 2014
8652913 Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss Feb. 18, 2014
8642429 Wide and deep oxide trench in a semiconductor substrate with interspersed vertical oxide ribs Feb. 4, 2014
8642431 N-type carrier enhancement in semiconductors Feb. 4, 2014
8642435 Performing treatment on stressors Feb. 4, 2014
8637871 Asymmetric hetero-structure FET and method of manufacture Jan. 28, 2014
8623713 Trench isolation structure Jan. 7, 2014
8609492 Vertical memory cell Dec. 17, 2013
8598003 Semiconductor device having doped epitaxial region and its methods of fabrication Dec. 3, 2013
8598009 Self-aligned embedded SiGe structure and method of manufacturing the same Dec. 3, 2013
8575621 Low interconnect resistance integrated switches Nov. 5, 2013
8569139 Method of manufacturing strained source/drain structures Oct. 29, 2013
8569846 MOS devices with improved source/drain regions with SiGe Oct. 29, 2013
8564025 Nanowire FET having induced radial strain Oct. 22, 2013
8552494 Semiconductor devices including elevated source and drain regions Oct. 8, 2013
8551831 Silicon germanium and polysilicon gate structure for strained silicon transistors Oct. 8, 2013
8551846 Methods for fabricating semiconductor devices Oct. 8, 2013
8546857 Semiconductor structure and method for forming the same Oct. 1, 2013
8536619 Strained MOS device and methods for forming the same Sep. 17, 2013
8524565 Semiconductor device and method for forming the same Sep. 3, 2013
8519916 Low interconnect resistance integrated switches Aug. 27, 2013
8501569 Semiconductor device having gradient doping profile Aug. 6, 2013
8497180 Transistor with boot shaped source/drain regions Jul. 30, 2013
8492259 Method of forming metal gate structure Jul. 23, 2013
8486794 Method for manufacturing semiconductor structure Jul. 16, 2013
8450775 Method to control source/drain stressor profiles for stress engineering May. 28, 2013
8445340 Sacrificial offset protection film for a FinFET device May. 21, 2013
8441000 Heterojunction tunneling field effect transistors, and methods for fabricating the same May. 14, 2013
8420464 Spacer as hard mask scheme for in-situ doping in CMOS finFETs Apr. 16, 2013
8409958 Method of manufacturing semiconductor device Apr. 2, 2013
8394691 Semiconductor devices having stressor regions and related fabrication methods Mar. 12, 2013
8383485 Epitaxial process for forming semiconductor devices Feb. 26, 2013
8377785 Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure Feb. 19, 2013
8361850 Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Jan. 29, 2013
8357576 Method of manufacturing semiconductor device Jan. 22, 2013
8357574 Method of fabricating epitaxial structures Jan. 22, 2013
8343826 Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys Jan. 1, 2013
8343872 Method of forming strained structures with compound profiles in semiconductor devices Jan. 1, 2013
8334185 Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer Dec. 18, 2012
8330231 Transistor having gate dielectric protection and structure Dec. 11, 2012
8329566 Method of manufacturing a high-performance semiconductor device Dec. 11, 2012
8329526 Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material Dec. 11, 2012
8319261 Semiconductor component structure with vertical dielectric layers Nov. 27, 2012
8313990 Nanowire FET having induced radial strain Nov. 20, 2012
8309991 Nanowire FET having induced radial strain Nov. 13, 2012
8304810 Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium Nov. 6, 2012

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