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Class Information
Number: 257/E21.431
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With an insulated gate (epo) > Lateral single gate silicon transistor (epo) > With source and drain recessed by etching or recessed and refi lled (epo)
Description: This subclass is indented under subclass E21.424. This subclass is substantially the same in scope as ECLA classification H01L21/336H8.


Patents under this class:
1 2 3 4 5

Patent Number Title Of Patent Date Issued
7608515 Diffusion layer for stressed semiconductor devices Oct. 27, 2009
7605042 SOI bottom pre-doping merged e-SiGe for poly height reduction Oct. 20, 2009
7605407 Composite stressors with variable element atomic concentrations in MOS devices Oct. 20, 2009
7601634 Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor Oct. 13, 2009
7601983 Transistor and method of manufacturing the same Oct. 13, 2009
7572705 Semiconductor device and method of manufacturing a semiconductor device Aug. 11, 2009
7569437 Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern Aug. 4, 2009
7566609 Method of manufacturing a semiconductor structure Jul. 28, 2009
7557396 Semiconductor device and method of manufacturing semiconductor device Jul. 7, 2009
7553718 Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps Jun. 30, 2009
7544528 Method for manufacturing substrate of liquid crystal device Jun. 9, 2009
7537988 Differential offset spacer May. 26, 2009
7538002 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors May. 26, 2009
7534689 Stress enhanced MOS transistor and methods for its fabrication May. 19, 2009
7504309 Pre-silicide spacer removal Mar. 17, 2009
7494884 SiGe selective growth without a hard mask Feb. 24, 2009
7485524 MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same Feb. 3, 2009
7482211 Junction leakage reduction in SiGe process by implantation Jan. 27, 2009
7479422 Semiconductor device with stressors and method therefor Jan. 20, 2009
7473591 Transistor with strain-inducing structure in channel Jan. 6, 2009
7446379 Transistor with dopant-bearing metal in source and drain Nov. 4, 2008
7413961 Method of fabricating a transistor structure Aug. 19, 2008
7413957 Methods for forming a transistor Aug. 19, 2008
7397091 SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material Jul. 8, 2008
7385261 Extended drain metal oxide semiconductor transistor and manufacturing method thereof Jun. 10, 2008
7381623 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance Jun. 3, 2008
7368792 MOS transistor with elevated source/drain structure May. 6, 2008
7364976 Selective etch for patterning a semiconductor film deposited non-selectively Apr. 29, 2008
7364957 Method and apparatus for semiconductor device with improved source/drain junctions Apr. 29, 2008
7361973 Embedded stressed nitride liners for CMOS performance improvement Apr. 22, 2008
7354835 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby Apr. 8, 2008
7344951 Surface preparation method for selective and non-selective epitaxial growth Mar. 18, 2008
7265419 Semiconductor memory device with cell transistors having electrically floating channel bodies to store data Sep. 4, 2007
7238561 Method for forming uniaxially strained devices Jul. 3, 2007
7223662 Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface May. 29, 2007
7195982 Method for manufacturing anti-punch through semiconductor device Mar. 27, 2007
7193276 Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer Mar. 20, 2007
7118952 Method of making transistor with strained source/drain Oct. 10, 2006
7118977 System and method for improved dopant profiles in CMOS transistors Oct. 10, 2006
7064039 Method to produce localized halo for MOS transistor Jun. 20, 2006
7061060 Offset-gate-type semiconductor device Jun. 13, 2006
7060576 Epitaxially deposited source/drain Jun. 13, 2006
7057216 High mobility heterojunction complementary field effect transistors and methods thereof Jun. 6, 2006
7045407 Amorphous etch stop for the anisotropic etching of substrates May. 16, 2006
7030465 Semiconductor device that can increase the carrier mobility and method for fabricating the same Apr. 18, 2006
7026214 Offset-gate-type semiconductor device Apr. 11, 2006
7026688 Field effect transistors having multiple stacked channels Apr. 11, 2006
7019326 Transistor with strain-inducing structure in channel Mar. 28, 2006
7009258 Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon Mar. 7, 2006
7002207 Field effect transistors having multiple stacked channels Feb. 21, 2006

1 2 3 4 5


 
 
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