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Class Information
Number: 257/E21.424
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With an insulated gate (epo) > Lateral single gate silicon transistor (epo)
Description: This subclass is indented under subclass E21.409. This subclass is substantially the same in scope as ECLA classification H01L21/336H.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.433 Where the source and drain or source and drain extensions are self-aligned to sides of gate (epo) 655
257/E21.428 With a recessed gate, e.g., lateral u-mos (epo) 151
257/E21.427 With asymmetry in channel direction, e.g., high-voltage lateral transistor with channel containing layer, e.g., p-base (epo) 602
257/E21.426 With single crystalline channel formed on the silicon substrate after insulating device isolation (epo) 133
257/E21.432 With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (epo) 114
257/E21.431 With source and drain recessed by etching or recessed and refi lled (epo) 376
257/E21.425 With source or drain region formed by schottky barrier or conductor-insulator-semiconductor structure (epo) 58


Patents under this class:
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Patent Number Title Of Patent Date Issued
8710587 Lateral double diffused metal oxide semiconductor device and method of manufacturing the same Apr. 29, 2014
8604524 Transistor design and layout for performance improvement with strain Dec. 10, 2013
8298898 Manufacturing method of semiconductor device with increased drain breakdown voltage Oct. 30, 2012
8212319 Semiconductor device comprising semiconductor film with recess Jul. 3, 2012
8173503 Fabrication of source/drain extensions with ultra-shallow junctions May. 8, 2012
8004035 Dual stress liner device and method Aug. 23, 2011
7999318 Heavily doped region in double-diffused source MOSFET (LDMOS) transistor and a method of fabricating the same Aug. 16, 2011
7973333 Lateral DMOS transistor and method for the production thereof Jul. 5, 2011
7935588 Enhanced transistor performance by non-conformal stressed layers May. 3, 2011
7737498 Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices Jun. 15, 2010
7670915 Contact liner in integrated circuit technology Mar. 2, 2010
7601623 Method of manufacturing a semiconductor device with a gate electrode having a laminate structure Oct. 13, 2009
7537997 Ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits May. 26, 2009
7514332 Semiconductor device and method for manufacturing the same Apr. 7, 2009
7482238 Method for manufacturing semiconductor device Jan. 27, 2009
7378318 System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits May. 27, 2008
6936517 Method for fabricating transistor of semiconductor device Aug. 30, 2005
6921940 MOS transistor and fabrication method thereof Jul. 26, 2005
6515319 Field-effect-controlled transistor and method for fabricating the transistor Feb. 4, 2003
6350641 Method of increasing the depth of lightly doping in a high voltage device Feb. 26, 2002
6329256 Self-aligned damascene gate formation with low gate resistance Dec. 11, 2001
6323524 Semiconductor device having a vertical active region and method of manufacture thereof Nov. 27, 2001
6225170 Self-aligned damascene gate with contact formation May. 1, 2001
6207513 Spacer process to eliminate corner transistor device Mar. 27, 2001
6144538 High voltage MOS transistor used in protection circuits Nov. 7, 2000
6140193 Method for forming a high-voltage semiconductor device with trench structure Oct. 31, 2000
6103589 High-voltage device substrate structure and method of fabrication Aug. 15, 2000
6104069 Semiconductor device having an elevated active region formed in an oxide trench Aug. 15, 2000
6083800 Method for fabricating high voltage semiconductor device Jul. 4, 2000
6078086 Metal oxide semiconductor field effect transistor and method of manufacturing the same Jun. 20, 2000
6054743 High voltage MOS transistor Apr. 25, 2000
6037229 High-voltage device substrate structure and method of fabrication Mar. 14, 2000
5998832 Metal oxide semiconductor device for an electro-static discharge circuit Dec. 7, 1999
5973379 Ferroelectric semiconductor device Oct. 26, 1999
5929484 High voltage semiconductor device Jul. 27, 1999
5897358 Semiconductor device having fluorine-enhanced transistor with elevated active regions and fabrication thereof Apr. 27, 1999
5872038 Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof Feb. 16, 1999
5851844 Ferroelectric semiconductor device and method of manufacture Dec. 22, 1998
5846862 Semiconductor device having a vertical active region and method of manufacture thereof Dec. 8, 1998
5811340 Metal oxide semiconductor field effect transistor and method of manufacturing the same Sep. 22, 1998
5804485 High density metal gate MOS fabrication process Sep. 8, 1998
5770880 P-collector H.V. PMOS switch VT adjusted source/drain Jun. 23, 1998
5734185 MOS transistor and fabrication process therefor Mar. 31, 1998
5646054 Method for manufacturing MOS transistor of high breakdown voltage Jul. 8, 1997
5571737 Metal oxide semiconductor device integral with an electro-static discharge circuit Nov. 5, 1996
5547903 Method of elimination of junction punchthrough leakage via buried sidewall isolation Aug. 20, 1996
5547895 Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions Aug. 20, 1996
5523246 Method of fabricating a high-voltage metal-gate CMOS device Jun. 4, 1996
5376568 Method of fabricating high voltage complementary metal oxide semiconductor transistors Dec. 27, 1994
5312766 Method of providing lower contact resistance in MOS transistors May. 17, 1994

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