Resources Contact Us Home
Browse by Category: Main > Physics
Class Information
Number: 257/E21.417
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for the manufacture of unipolar device (epo) > Field-effect transistor (epo) > With an insulated gate (epo) > With channel containing layer, e.g., p-base, fo rmed in or on drain region, e.g., dmos transistor (epo)
Description: This subclass is indented under subclass E21.409. This subclass is substantially the same in scope as ECLA classification H01L21/336B.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.418 Vertical power dmos transistor (epo) 409

Patents under this class:
1 2 3 4 5

Patent Number Title Of Patent Date Issued
5719423 Isolated power transistor Feb. 17, 1998
5591657 Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking Jan. 7, 1997
5585294 Method of fabricating lateral double diffused MOS (LDMOS) transistors Dec. 17, 1996
5510275 Method of making a semiconductor device with a composite drift region composed of a substrate and a second semiconductor material Apr. 23, 1996
5508547 LDMOS transistor with reduced projective area of source region Apr. 16, 1996
5482888 Method of manufacturing a low resistance, high breakdown voltage, power MOSFET Jan. 9, 1996
5466616 Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up Nov. 14, 1995
5466616 Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up Nov. 14, 1995
5444002 Method of fabricating a short-channel DMOS transistor with removable sidewall spacers Aug. 22, 1995
5434435 Trench gate lateral MOSFET Jul. 18, 1995
5407844 Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor Apr. 18, 1995
5404043 Semiconductor devices of the planar type bipolar transistors and combination bipolar/MIS type transistors Apr. 4, 1995
5369045 Method for forming a self-aligned lateral DMOS transistor Nov. 29, 1994
5349224 Integrable MOS and IGBT devices having trench gate structure Sep. 20, 1994
5281544 Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors Jan. 25, 1994
5275961 Method of forming insulated gate field-effect transistors Jan. 4, 1994
5132235 Method for fabricating a high voltage MOS transistor Jul. 21, 1992
5023678 High power MOSFET and integrated control circuit therefor for high-side switch application Jun. 11, 1991
4904614 Method of manufacturing lateral IGFETS including reduced surface field regions Feb. 27, 1990
4892838 Method of manufacturing an insulated gate field effect transistor Jan. 9, 1990
4866495 High power MOSFET and integrated control circuit therefor for high-side switch application Sep. 12, 1989
4738936 Method of fabrication lateral FET structure having a substrate to source contact Apr. 19, 1988
4682405 Methods for forming lateral and vertical DMOS transistors Jul. 28, 1987
4625388 Method of fabricating mesa MOSFET using overhang mask and resulting structure Dec. 2, 1986
4561168 Method of making shadow isolated metal DMOS FET device Dec. 31, 1985
4442589 Method for manufacturing field effect transistors Apr. 17, 1984
4404576 All implanted MOS transistor Sep. 13, 1983
4261761 Method of manufacturing sub-micron channel width MOS transistor Apr. 14, 1981
4217599 Narrow channel MOS devices and method of manufacturing Aug. 12, 1980
4190850 MIS field effect transistor having a short channel length Feb. 26, 1980
4173818 Method for fabricating transistor structures having very short effective channels Nov. 13, 1979
4119996 Complementary DMOS-VMOS integrated circuit structure Oct. 10, 1978
4078947 Method for forming a narrow channel length MOS field effect transistor Mar. 14, 1978
4062699 Method for fabricating diffusion self-aligned short channel MOS device Dec. 13, 1977
4058822 High voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device and manufacture thereof Nov. 15, 1977
4001048 Method of making metal oxide semiconductor structures using ion implantation Jan. 4, 1977

1 2 3 4 5

  Recently Added Patents
System for thermally controlling displays
Digital fine delay processing
Wine cellar alarm system
Real-image zoom viewfinder and imaging apparatus
Dynamic reconstruction of a calibration state of an absorption spectrometer
  Randomly Featured Patents
Method of compensating tilt using two-axis geomagnetic sensor, and acceleration sensor, and apparatus thereof
Fixed bearing assembly for a tiltable-converter carrying trunnion
Optical communication network and protection methods
System for teaching visual discrimination of spatially oriented subject matter
Power control method and apparatus for fusing roller of eletrophotographic image forming apparatus
Method for separation of an ester from a reaction mixture
Torque ripple sensor and mitigation mechanism
Light metal cylinder head for a valve-controlled internal combustion engine
Digital thermal printing process
Unitary absorbent core with binding agents