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Class Information
Number: 257/E21.378
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Multi-step process for manufacture of device of bipolar type, e.g., diodes, transistors, thyristors, resistors, capacitors) (epo) > Device comprising three or more electrodes (epo) > Transistor (epo) > Silicon vertical transistor (epo) > Inverse transistor (epo)
Description: This subclass is indented under subclass E21.375. This subclass is substantially the same in scope as ECLA classification H01L21/331F4.










Patents under this class:

Patent Number Title Of Patent Date Issued
8513717 Semiconductor device and method for manufacturing the same Aug. 20, 2013
7611956 Semiconductor device having MOS varactor and methods for fabricating the same Nov. 3, 2009
5443994 Method of fabricating a semiconductor device having a borosilicate glass spacer Aug. 22, 1995
5242854 High performance semiconductor devices and their manufacture Sep. 7, 1993
5139961 Reducing base resistance of a BJT by forming a self aligned silicide in the single crystal region of the extrinsic base Aug. 18, 1992
5045483 Self-aligned silicided base bipolar transistor and resistor and method of fabrication Sep. 3, 1991
5037768 Method of fabricating a double polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors Aug. 6, 1991
4757027 Method for fabricating improved oxide defined transistors Jul. 12, 1988
4326212 Structure and process for optimizing the characteristics of I.sup.2 L devices Apr. 20, 1982











 
 
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