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Class Information
Number: 257/E21.345
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Radiation treatment (epo) > With high-energy radiation (epo) > Producing ions for implantation (epo) > Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (epo)
Description: This subclass is indented under subclass E21.334. This subclass is substantially the same in scope as ECLA classification H01L21/265F.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6225151 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion May. 1, 2001
6218250 Method and apparatus for minimizing parasitic resistance of semiconductor devices Apr. 17, 2001
6215148 NROM cell with improved programming, erasing and cycling Apr. 10, 2001
6207482 Integration method for deep sub-micron dual gate transistor design Mar. 27, 2001
6204132 Method of forming a silicide layer using an angled pre-amorphization implant Mar. 20, 2001
6204128 Method for fabricating semiconductor device Mar. 20, 2001
6200870 Method for forming gate Mar. 13, 2001
6201282 Two bit ROM cell and process for producing same Mar. 13, 2001
6198128 Method of manufacturing a semiconductor device, and semiconductor device Mar. 6, 2001
6194278 Device performance by employing an improved method for forming halo implants Feb. 27, 2001
6194293 Channel formation after source and drain regions are formed Feb. 27, 2001
6190980 Method of tilted implant for pocket, halo and source/drain extension in ULSI dense structures Feb. 20, 2001
6187643 Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI) Feb. 13, 2001
6180441 Bar field effect transistor Jan. 30, 2001
6180464 Metal oxide semiconductor device with localized laterally doped channel Jan. 30, 2001
6180470 FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements Jan. 30, 2001
6180471 Method of fabricating high voltage semiconductor device Jan. 30, 2001
6177314 Method of manufacturing a semiconductor device comprising a field effect transistor Jan. 23, 2001
6174773 Method of manufacturing vertical trench misfet Jan. 16, 2001
6174778 Method of fabricating metal oxide semiconductor Jan. 16, 2001
6172401 Transistor device configurations for high voltage applications and improved device performance Jan. 9, 2001
6172399 Formation of ultra-shallow semiconductor junction using microwave annealing Jan. 9, 2001
6171913 Process for manufacturing a single asymmetric pocket implant Jan. 9, 2001
6163053 Semiconductor device having opposite-polarity region under channel Dec. 19, 2000
6162692 Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor Dec. 19, 2000
6159783 Semiconductor device having MOS transistor and method of manufacturing the same Dec. 12, 2000
6153484 Etching process of CoSi.sub.2 layers Nov. 28, 2000
6150670 Process for fabricating a uniform gate oxide of a vertical transistor Nov. 21, 2000
6146944 Large angle implantation to prevent field turn-on under select gate transistor field oxide region for non-volatile memory devices Nov. 14, 2000
6147383 LDD buried channel field effect semiconductor device and manufacturing method Nov. 14, 2000
6144072 Semiconductor device formed on insulating layer and method of manufacturing the same Nov. 7, 2000
6140679 Zero thermal budget manufacturing process for MOS-technology power devices Oct. 31, 2000
6133124 Device improvement by source to drain resistance lowering through undersilicidation Oct. 17, 2000
6133123 Fabrication of semiconductor gettering structures by ion implantation Oct. 17, 2000
6130134 Method for forming asymmetric flash EEPROM with a pocket to focus electron injections Oct. 10, 2000
6127248 Fabrication method for semiconductor device Oct. 3, 2000
6127717 Totally self-aligned transistor with polysilicon shallow trench isolation Oct. 3, 2000
6121096 Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer Sep. 19, 2000
6114210 Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime Sep. 5, 2000
6110786 Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof Aug. 29, 2000
6103578 Method for forming high breakdown semiconductor device Aug. 15, 2000
6100013 Method for forming transistors with raised source and drains and device formed thereby Aug. 8, 2000
6100159 Quasi soi device Aug. 8, 2000
6096586 MOS device with self-compensating V.sub.aT -implants Aug. 1, 2000
6096641 Method of manufacturing semiconductor device Aug. 1, 2000
6091118 Semiconductor device having reduced overlap capacitance and method of manufacture thereof Jul. 18, 2000
6087706 Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls Jul. 11, 2000
6087237 Method of manufacturing a MOSFET by forming a single oxide layer doping with either an oxide accelerator or an oxide inhibitor producing asymmetric thickness Jul. 11, 2000
6087210 Method of manufacturing a CMOS Transistor Jul. 11, 2000
6083795 Large angle channel threshold implant for improving reverse narrow width effect Jul. 4, 2000

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