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Class Information
Number: 257/E21.345
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Radiation treatment (epo) > With high-energy radiation (epo) > Producing ions for implantation (epo) > Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (epo)
Description: This subclass is indented under subclass E21.334. This subclass is substantially the same in scope as ECLA classification H01L21/265F.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent Number Title Of Patent Date Issued
6465844 Power semiconductor device and method of manufacturing the same Oct. 15, 2002
6461946 Method of manufacturing semiconductor device Oct. 8, 2002
6461908 Method of manufacturing a semiconductor device Oct. 8, 2002
6458666 Spot-implant method for MOS transistor applications Oct. 1, 2002
6458665 Halo ion implantation method for fabricating a semiconductor device Oct. 1, 2002
6455388 Method of manufacturing metal-oxide semiconductor transistor Sep. 24, 2002
6448120 Totally self-aligned transistor with tungsten gate Sep. 10, 2002
6448142 Method for fabricating a metal oxide semiconductor transistor Sep. 10, 2002
6448613 Fabrication of a field effect transistor with minimized parasitic Miller capacitance Sep. 10, 2002
6444548 Bitline diffusion with halo for improved array threshold voltage control Sep. 3, 2002
6440812 Angled implant to improve high current operation of bipolar transistors Aug. 27, 2002
6437406 Super-halo formation in FETs Aug. 20, 2002
6432781 Inverted MOSFET process Aug. 13, 2002
6429082 Method of manufacturing a high voltage using a latid process for forming a LDD Aug. 6, 2002
6426262 Method of analyzing the effects of shadowing of angled halo implants Jul. 30, 2002
6426258 Method of manufacturing a semiconductor integrated circuit device Jul. 30, 2002
6420766 Transistor having raised source and drain Jul. 16, 2002
6417082 Semiconductor structure Jul. 9, 2002
6417064 Method for treating the surface of a deep trench Jul. 9, 2002
6414354 Semiconductor device having a semiconductor layer with a channel region having a continuously increasing impurity concentration profile Jul. 2, 2002
6410393 Semiconductor device with asymmetric channel dopant profile Jun. 25, 2002
6410967 Transistor having enhanced metal silicide and a self-aligned gate electrode Jun. 25, 2002
6410382 Fabrication method of semiconductor device Jun. 25, 2002
6406964 Method of controlling junction recesses in a semiconductor device Jun. 18, 2002
6403426 Method of manufacturing a semiconductor device Jun. 11, 2002
6396103 Optimized single side pocket implant location for a field effect transistor May. 28, 2002
6391730 Process for fabricating shallow pocket regions in a non-volatile semiconductor device May. 21, 2002
6387766 Method for manufacturing an integrated circuit with low threshold voltage differences of the transistors therein May. 14, 2002
6380041 Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor Apr. 30, 2002
6376276 Method of preparing diamond semiconductor Apr. 23, 2002
6373119 Semiconductor device and method of manufacturing the same Apr. 16, 2002
6372587 Angled halo implant tailoring using implant mask Apr. 16, 2002
6373108 Semiconductor device having reduced sheet resistance of source/drain regions Apr. 16, 2002
6373102 Process for fabricating a channel region of a transistor device with ion implantation and the transistor device formed therefrom Apr. 16, 2002
6369425 High-density power device Apr. 9, 2002
6369434 Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors Apr. 9, 2002
6362062 Disposable sidewall spacer process for integrated circuits Mar. 26, 2002
6358783 Semiconductor device and method of manufacturing the same Mar. 19, 2002
6355963 MOS type semiconductor device having an impurity diffusion layer Mar. 12, 2002
6355528 Method to form narrow structure using double-damascene process Mar. 12, 2002
6352912 Reduction of reverse short channel effects by deep implantation of neutral dopants Mar. 5, 2002
6350656 SEG combined with tilt side implant process Feb. 26, 2002
6348711 NROM cell with self-aligned programming and erasure areas Feb. 19, 2002
6348388 Process for fabricating a uniform gate oxide of a vertical transistor Feb. 19, 2002
6346441 Method of fabricating flash memory cell using two tilt implantation steps Feb. 12, 2002
6344405 Transistors having optimized source-drain structures and methods for making the same Feb. 5, 2002
6344677 Semiconductor device comprising MIS field-effect transistor, and method of fabricating the same Feb. 5, 2002
6337504 Insulated gate transistor with leakage current prevention feature Jan. 8, 2002
6329235 Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM Dec. 11, 2001
6329257 Method for laterally peaked source doping profiles for better erase control in flash memory devices Dec. 11, 2001

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