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Class Information
Number: 257/E21.345
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Radiation treatment (epo) > With high-energy radiation (epo) > Producing ions for implantation (epo) > Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (epo)
Description: This subclass is indented under subclass E21.334. This subclass is substantially the same in scope as ECLA classification H01L21/265F.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent Number Title Of Patent Date Issued
5731233 Semiconductor device having MOS transistor and method of manufacturing the same Mar. 24, 1998
5731214 Manufacture of semiconductor device with self-aligned doping Mar. 24, 1998
5728611 Method of fabricating semiconductor device Mar. 17, 1998
5726069 Use of oblique implantation in forming emitter of bipolar transistor Mar. 10, 1998
5719082 Angled implant to improve high current operation of bipolar transistors Feb. 17, 1998
5712204 Method of making a semiconductor device having reduced junction capacitance between the source and drain regions and the substrate Jan. 27, 1998
5705410 Method of producing a semi-conductor with a highly doped zone situated between lightly doped zones, for the manufacture of transistors Jan. 6, 1998
5686324 Process for forming LDD CMOS using large-tilt-angle ion implantation Nov. 11, 1997
5684317 MOS transistor and method of manufacturing thereof Nov. 4, 1997
5675172 Metal-insulator-semiconductor device having reduced threshold voltage and high mobility for high speed/low-voltage operation Oct. 7, 1997
5670392 Process for manufacturing high-density MOS-technology power devices Sep. 23, 1997
5668026 DMOS fabrication process implemented with reduced number of masks Sep. 16, 1997
5668018 Method for defining a region on a wall of a semiconductor structure Sep. 16, 1997
5635749 High performance field effect transistor with lai region Jun. 3, 1997
5631485 ESD and hot carrier resistant integrated circuit structure May. 20, 1997
5624859 Method for providing device isolation and off-state leakage current for a semiconductor device Apr. 29, 1997
5610430 Semiconductor device having reduced gate overlapping capacitance Mar. 11, 1997
5606191 Semiconductor device with lightly doped drain regions Feb. 25, 1997
5593907 Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices Jan. 14, 1997
5578508 Vertical power MOSFET and process of fabricating the same Nov. 26, 1996
5576227 Process for fabricating a recessed gate MOS device Nov. 19, 1996
5565700 Surface counter doped N-LDD for high carrier reliability Oct. 15, 1996
5554871 Semiconductor device having MOS transistor with nitrogen doping Sep. 10, 1996
5554544 Field edge manufacture of a T-gate LDD pocket device Sep. 10, 1996
5543337 Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants Aug. 6, 1996
5543654 Contoured-tub fermi-threshold field effect transistor and method of forming same Aug. 6, 1996
5536957 MOS field effect transistor having source/drain regions surrounded by impurity wells Jul. 16, 1996
5532508 Semiconductor device with LDD structure Jul. 2, 1996
5525822 Fermi threshold field effect transistor including doping gradient regions Jun. 11, 1996
5518949 Electrical isolation method for devices made on SOI wafer May. 21, 1996
5516711 Method for forming LDD CMOS with oblique implantation May. 14, 1996
5516707 Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor May. 14, 1996
5512498 Method of producing semiconductor device Apr. 30, 1996
5512771 MOS type semiconductor device having a low concentration impurity diffusion region Apr. 30, 1996
5510279 Method of fabricating an asymmetric lightly doped drain transistor device Apr. 23, 1996
5508212 Salicide process for a MOS semiconductor device using nitrogen implant of titanium Apr. 16, 1996
5498556 Metal-oxide-semiconductor field-effect transistor and its method of fabrication Mar. 12, 1996
5496751 Method of forming an ESD and hot carrier resistant integrated circuit structure Mar. 5, 1996
5488004 SOI by large angle oxygen implant Jan. 30, 1996
5478763 High performance field effect transistor and method of manufacture thereof Dec. 26, 1995
5472895 Method for manufacturing a transistor of a semiconductor device Dec. 5, 1995
5466957 Transistor having source-to-drain nonuniformly-doped channel and method for fabricating the same Nov. 14, 1995
5459085 Gate array layout to accommodate multi angle ion implantation Oct. 17, 1995
RE35036 Method of making symmetrically controlled implanted regions using rotational angle of the substrate Sep. 12, 1995
5449937 Field effect transistor with short channel and manufacturing method therefor Sep. 12, 1995
5444007 Formation of trenches having different profiles Aug. 22, 1995
5439835 Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough Aug. 8, 1995
5440160 High saturation current, low leakage current fermi threshold field effect transistor Aug. 8, 1995
5432107 Semiconductor fabricating method forming channel stopper with diagonally implanted ions Jul. 11, 1995
5426063 Method of making a field effect transistor with submicron channel length and threshold implant using oblique implantation Jun. 20, 1995

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