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Class Information
Number: 257/E21.345
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Radiation treatment (epo) > With high-energy radiation (epo) > Producing ions for implantation (epo) > Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (epo)
Description: This subclass is indented under subclass E21.334. This subclass is substantially the same in scope as ECLA classification H01L21/265F.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent Number Title Of Patent Date Issued
6083794 Method to perform selective drain engineering with a non-critical mask Jul. 4, 2000
6078086 Metal oxide semiconductor field effect transistor and method of manufacturing the same Jun. 20, 2000
6078081 Semiconductor device for improving short channel effect Jun. 20, 2000
6071781 Method of fabricating lateral MOS transistor Jun. 6, 2000
6066885 Subtrench conductor formed with large tilt angle implant May. 23, 2000
6060733 Formation of lightly doped regions under a gate having a reduced gate oxide May. 9, 2000
6057191 Process for the fabrication of integrated circuits with contacts self-aligned to active areas May. 2, 2000
6051468 Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance Apr. 18, 2000
6051483 Formation of ultra-shallow semiconductor junction using microwave annealing Apr. 18, 2000
6049114 Semiconductor device having a metal containing layer overlying a gate dielectric Apr. 11, 2000
6048784 Transistor having an improved salicided gate and method of construction Apr. 11, 2000
6043130 Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base Mar. 28, 2000
6040600 Trenched high breakdown voltage semiconductor device Mar. 21, 2000
6040212 Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage Mar. 21, 2000
6040208 Angled ion implantation for selective doping Mar. 21, 2000
6037231 Method for forming a MOS structure having sidewall source/drain and embedded gate Mar. 14, 2000
6037200 Compound semiconductor device and fabrication method Mar. 14, 2000
6034398 Semiconductor device and manufacturing method of the same Mar. 7, 2000
6030869 Method for fabricating nonvolatile semiconductor memory device Feb. 29, 2000
6030871 Process for producing two bit ROM cell utilizing angled implant Feb. 29, 2000
6030875 Method for making semiconductor device having nitrogen-rich active region-channel interface Feb. 29, 2000
6031268 Complementary semiconductor device and method for producing the same Feb. 29, 2000
6031272 MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region Feb. 29, 2000
6020228 CMOS device structure with reduced short channel effect and memory capacitor Feb. 1, 2000
6020244 Channel dopant implantation with automatic compensation for variations in critical dimension Feb. 1, 2000
6017793 Method of forming a memory cell of a nonvolatile semiconductor memory device Jan. 25, 2000
6010936 Semiconductor device fabrication method Jan. 4, 2000
6010952 Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation Jan. 4, 2000
6008094 Optimization of logic gates with criss-cross implants to form asymmetric channel regions Dec. 28, 1999
6008099 Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion Dec. 28, 1999
6002150 Compound material T gate structure for devices with gate dielectrics having a high dielectric constant Dec. 14, 1999
5981148 Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby Nov. 9, 1999
5982022 Angled implant to improve high current operation of transistors Nov. 9, 1999
5981996 Vertical trench misfet and method of manufacturing the same Nov. 9, 1999
5976960 Method of forming an electrically conductive substrate interconnect continuity region with an angled implant Nov. 2, 1999
5976937 Transistor having ultrashallow source and drain junctions with reduced gate overlap and method Nov. 2, 1999
5976768 Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby Nov. 2, 1999
5973361 DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness Oct. 26, 1999
5972745 Method or forming self-aligned halo-isolated wells Oct. 26, 1999
5970353 Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion Oct. 19, 1999
5970330 Method of making field effect transistor with higher mobility Oct. 19, 1999
5966604 Method of manufacturing MOS components having lightly doped drain structures Oct. 12, 1999
5963801 Method of forming retrograde well structures and punch-through barriers using low energy implants Oct. 5, 1999
5960291 Asymmetric channel transistor and method for making same Sep. 28, 1999
5956590 Process of forming a field effect transistor without spacer mask edge defects Sep. 21, 1999
5943576 Angled implant to build MOS transistors in contact holes Aug. 24, 1999
5940711 Method for making high-frequency bipolar transistor Aug. 17, 1999
5936277 MOS transistor with impurity-implanted region Aug. 10, 1999
5936285 Gate array layout to accommodate multi-angle ion implantation Aug. 10, 1999
5937293 Method of fabricating a source/drain with LDD and halo Aug. 10, 1999

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