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Class Information
Number: 257/E21.244
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic technique (epo) > Post-treatment (epo) > Planarization of insulating layer (epo) > Involving dielectric removal step (epo)
Description: This subclass is indented under subclass E21.243. This subclass is substantially the same in scope as ECLA classification H01L21/3105B2.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.245 Removal by chemical etching, e.g., dry etching (epo) 304

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Patent Number Title Of Patent Date Issued
6261922 Methods of forming trench isolation regions Jul. 17, 2001
6261914 Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer Jul. 17, 2001
6261851 Optimization of CMP process by detecting of oxide/nitride interface using IR system Jul. 17, 2001
6258205 Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material Jul. 10, 2001
6258711 Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers Jul. 10, 2001
6255151 Semiconductor integrated circuit device and method of manufacturing same Jul. 3, 2001
6254457 Process for polishing wafers of integrated circuits Jul. 3, 2001
6255211 Silicon carbide stop layer in chemical mechanical polishing over metallization layers Jul. 3, 2001
6251788 Method of integrated circuit polishing without dishing effects Jun. 26, 2001
6251772 Dielectric adhesion enhancement in damascene process for semiconductors Jun. 26, 2001
6251783 Method of manufacturing shallow trench isolation Jun. 26, 2001
6251784 Real-time control of chemical-mechanical polishing processing by monitoring ionization current Jun. 26, 2001
6248667 Chemical mechanical polishing method using double polishing stop layer Jun. 19, 2001
6242343 Process for fabricating semiconductor device and apparatus for fabricating semiconductor device Jun. 5, 2001
6242352 Method of preventing micro-scratches on the surface of a semiconductor wafer when performing a CMP process Jun. 5, 2001
6239032 Polishing method May. 29, 2001
6234877 Method of chemical mechanical polishing May. 22, 2001
6235608 STI process by method of in-situ multilayer dielectric deposition May. 22, 2001
6235636 Resist removal by polishing May. 22, 2001
6232043 Rule to determine CMP polish time May. 15, 2001
6232174 Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film May. 15, 2001
6228280 Endpoint detection by chemical reaction and reagent May. 8, 2001
6228727 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess May. 8, 2001
6224464 Polishing method and polisher used in the method May. 1, 2001
6224466 Methods of polishing materials, methods of slowing a rate of material removal of a polishing process May. 1, 2001
6221560 Method to enhance global planarization of silicon oxide surface for IC device fabrication Apr. 24, 2001
6221773 Method for working semiconductor wafer Apr. 24, 2001
6218286 Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process Apr. 17, 2001
6218307 Method of fabricating shallow trench isolation structure Apr. 17, 2001
6218735 Process to improve adhesion of cap layers in intergrated circuits Apr. 17, 2001
6218285 Method for forming inter-metal dielectric layers in metallization process Apr. 17, 2001
6214734 Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection Apr. 10, 2001
6213847 Semiconductor wafer polishing device and polishing method thereof Apr. 10, 2001
6213844 Method for obtaining a desired film thickness using chemical mechanical polishing Apr. 10, 2001
6211086 Method of avoiding CMP caused residue on wafer edge uncompleted field Apr. 3, 2001
6211097 Planarization process Apr. 3, 2001
6211088 Manufacturing method for semiconductor gas-phase epitaxial wafer Apr. 3, 2001
6207554 Gap filling process in integrated circuits using low dielectric constant materials Mar. 27, 2001
6207630 Processing compositions and methods of using same Mar. 27, 2001
6204195 Method to prevent CMP overpolish Mar. 20, 2001
6203404 Chemical mechanical polishing methods Mar. 20, 2001
6204184 Method of manufacturing semiconductor devices Mar. 20, 2001
6200901 Polishing polymer surfaces on non-porous CMP pads Mar. 13, 2001
6200653 Method of forming an intermetal dielectric layer Mar. 13, 2001
6200896 Employing an acidic liquid and an abrasive surface to polish a semiconductor topography Mar. 13, 2001
6200897 Method for manufacturing even dielectric layer Mar. 13, 2001
6197660 Integration of CMP and wet or dry etching for STI Mar. 6, 2001
6197691 Shallow trench isolation process Mar. 6, 2001
6194299 Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon Feb. 27, 2001
6191037 Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes Feb. 20, 2001

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