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Class Information
Number: 257/E21.243
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of semiconductor device (epo) > Device having at least one potential-jump barrier or surface barrier, e.g., pn junction, depletion layer, carrier concentration layer (epo) > Device having semiconductor body comprising group iv elements or group iii-v compounds with or without impurities, e.g., doping materials (epo) > Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (epo) > To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (epo) > To form insulating layer thereon, e.g., for masking or by using photolithographic technique (epo) > Post-treatment (epo) > Planarization of insulating layer (epo)
Description: This subclass is indented under subclass E21.241. This subclass is substantially the same in scope as ECLA classification H01L21/3105B.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.244 Involving dielectric removal step (epo) 942


Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
4735917 Silicon-on-sapphire integrated circuits Apr. 5, 1988
4732658 Planarization of silicon semiconductor devices Mar. 22, 1988
4732761 Thin film forming apparatus and method Mar. 22, 1988
4690746 Interlayer dielectric process Sep. 1, 1987
4544576 Deep dielectric isolation by fused glass Oct. 1, 1985
4539744 Semiconductor planarization process and structures made thereby Sep. 10, 1985
4510173 Method for forming flattened film Apr. 9, 1985
4504333 Method of making field oxide regions Mar. 12, 1985
4492717 Method for forming a planarized integrated circuit Jan. 8, 1985

1 2 3 4 5 6










 
 
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